TCI6630K2L Datasheet, PDF (284/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
• Trace Sinks
– Support for trace export (from all processor cores and DEBUGSS STM) through emulation pins.
Concurrent trace of DSP and STM traces or ARM and STM traces via EMU pins is possible.
Concurrent trace export of DSP and ARM is not possible via EMU pins.
– Support for 32KB DEBUGSS TBR (Trace Buffer and Router) to hold system trace. The data can be
drained using EDMA to on-chip or DDR memory buffers. These intermediate buffers can
subsequently be drained through the device high speed interfaces. The DEBUGSS TBR is
dedicated to the DEBUGSS STM module. The trace draining interface used in KeyStone II for
DEBUGSS and ARMSS are based on the new CT-TBR.
• Cross triggering: Provides a way to propagate debug (trigger) events from one
processor/subsystem/module to another
– Cross triggering between multiple devices via EMU0/EMU1 pins
– Cross triggering between multiple processing cores within the device like ARM/DSPCores and non-
processor entities like ARM STM (input only), CPTracers, CT-TBRs and DEBUGSS STM (input
only)
• Synchronized starting and stopping of processing cores
– Global start of all ARM cores
– Global start of all DSP cores
– Global stopping of all ARMand DSP cores
• Emulation mode aware peripherals (suspend features and debug access features)
• Support system memory access via the DAP port (natively support 32-bit address, and it can support
36-bit address through configuration of MPAX inside MSMC). Debug access to any invalid memory
location (reserved/clock-gated/power-down) does not cause system hang.
• Scan access to secondary TAPs of DEBUGSS is disabled in Secure devices by default. Security
override sequence is supported (requires software override sequence) to enable debug in secure
devices. In addition, Debug features of the ARM cores are blockable through the ARM debug
authentication interface in secure devices.
• Support WIR (wait-in-reset) debug boot mode for Non-secure devices.
• Debug functionality survives all pin resets except power-on resets (POR/RESETFULL) and test reset
(TRST).
• PDSP Debug features like access/control through DAP, Halt mode debug and software
instrumentation.
11.36.1.1 ARM Subsystem Features
• Support for invasive debug like halt mode debugging (breakpoint, watchpoints) and monitor mode
debugging
• Support for non-invasive debugging (program trace, performance monitoring)
• Support for A15 Performance Monitoring Unit (cycle counters)
• Support for per core CoreSight™ Program Trace Module (CS-PTM) with timing
• Support for an integrated CoreSight System Trace Module (CS-STM) for hardware event and software
instrumentation
• A shared timestamp counter for all ARM cores and STM is integrated in ARMSS for trace data
correlation
• Support for a 16KB Trace Buffer and Router (TBR) to hold PTM/STM trace. The trace data is copied
by EDMA to external memory for draining by device high speed serial interfaces.
• Support for simultaneous draining of trace stream through EMUn pins and TBR (to achieve higher
aggregate trace throughput)
• Support for debug authentication interface to disable debug accesses in secure devices
• Support for cross triggering between MPU cores, CS-STM and CT-TBR
• Support for debug through warm reset
284 TCI6630K2L Peripheral Information and Electrical Specifications
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