TCI6630K2L Datasheet, PDF (283/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
EM_CE[3:0]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_OE
EM_WAIT
Setup
Strobe
Extended Due to EM_WAIT
Strobe Hold
2
Asserted
14
11
2
Deasserted
Figure 11-67. EMIF16 EM_WAIT Read Timing Diagram
EM_CE[3:0]
Setup
Strobe
Extended Due to EM_WAIT
Strobe Hold
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_WE
EM_WAIT
2
Asserted
28
25
2
Deasserted
Figure 11-68. EMIF16 EM_WAIT Write Timing Diagram
11.36 Emulation Features and Capability
The debug capabilities of KeyStone II devices include the Debug subsystem module (DEBUGSS). The
DEBUGSS module contains the ICEPick module which handles the external JTAG Test Access Port
(TAP) and multiple secondary TAPs for the various processing cores of the device. It also provides Debug
Access Port (DAP) for system wide memory access from debugger, Cross triggering, System trace,
Peripheral suspend generation, Debug port (EMUx) pin management etc. The DEBUGSS module works in
conjunction with the debug capability integrated in the processing cores (ARM and DSP subsystems)to
provide a comprehensive hardware platform for a rich debug and development experience.
11.36.1 Chip Level Features
• Support for 1149.1(JTAG and Boundary scan) and 1149.6 (Boundary scan extensions).
• Trace sources to DEBUG SubSystem System Trace Module (DEBUGSS STM)
– Provides a way for hardware instrumentation and software messaging to supplement the processor
core trace mechanisms.
– Hardware instrumentation support of CPTracers to support logging of bus transactions for critical
endpoints
– Software messaging/instrumentation support for SoC and QMSS PDSP cores through DEBUGSS
STM.
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TCI6630K2L Peripheral Information and Electrical Specifications 283
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