TCI6630K2L Datasheet, PDF (224/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
11.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power
dissipation. The Global Power Sleep Controller (GPSC) is used to control the power gating of various
power domains.
The following table shows the TCI6630K2L power domains.
DOMAIN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BLOCK(S)
Most peripheral logic (BOOTCFG,
EMIF16, I²C, INTC, GPIO, USB,
USIM)
Per-core TETB and system TETB
Network Coprocessor
PCIe0
PCIe1
DFE__PD2
Smart Reflex
MSMC RAM
C66x Core 0, L1/L2 RAMs
C66x Core 1, L1/L2 RAMs
C66x Core 2, L1/L2 RAMs
C66x Core 3, L1/L2 RAMs
Reserved
Reserved
Reserved
Reserved
EMIF(DDR3A)
RAC_0 and TAC
DFE_PD0
FFTC_0
Reserved
OSR (On Chip Standalone RAM)
TCP3d_0
TCP3d_1
VCP2_0, VCP2_1, VCP2_2, and
VCP2_3
Reserved
BCP
DFE_PD1
FFTC_1
IQN_AIL
Reserved
ARM CorePac
Table 11-6. Power Domains
NOTE
Cannot be disabled
RAMs can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
MSMC RAM can be powered down
L2 RAMs can sleep
L2 RAMs can sleep
L2 RAMs can sleep
L2 RAMs can sleep
Logic can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
RAMs can be powered down
RAMs can be powered down
RAMs can be powered down
RAMs can be powered down
Reserved
Logic can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
POWER CONNECTION
Always on
Software control
Software control
Software control
Software control
Software control
Software control
Software control via C66x CorePac. For
details, see the TMS320C66x DSP CorePac
User's Guide (SPRUGW0).
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Reserved
Software control
Software control
Software control
Software control
Software control
11.3.2 Clock Domains
Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each
module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL
controller to enable and disable that module's clock(s) at the source. For modules that share a clock with
other modules, the LPSC controls the clock gating logic for each module.
Table 11-7 shows the TCI6630K2L clock domains.
224 TCI6630K2L Peripheral Information and Electrical Specifications
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