TCI6630K2L Datasheet, PDF (159/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
• Secure ROM Boot when the C66x CorePac0 is the boot master —The C66x CorePac0 and the
ARM CorePac Core0 are released from reset simultaneously and the C66x CorePac0 begins
executing from secure ROM. The C66x CorePac0 performs the boot process including any
authentication and decryption required on the bootloaded image for the C66x CorePacs and for the
ARM CorePac prior to beginning execution.
• Secure ROM Boot when the ARM CorePac0 is the boot master — The C66x CorePac0 and the
ARM CorePac Core0 are released from reset simultaneously and begin executing from secure ROM.
The ARM CorePac Core0 initiates the boot process. The C66x CorePac0 performs any authentication
and decryption required on the bootloaded image for the C66x CorePacs and ARM CorePac prior to
beginning execution.
The boot process performed by the C66x CorePac0 and the ARM CorePac Core0 in public ROM boot and
secure ROM boot are determined by the BOOTMODE[15:0] value in the DEVSTAT register. The C66x
CorePac0 and the ARM CorePac Core0 read this value, and then execute the associated boot process in
software. Bit 8 determines whether the boot is C66x CorePac boot or ARM CorePac boot. The figure
below shows the bits associated with BOOTMODE[15:0] (DEVSTAT[16:1]) when the C66x CorePac or
ARM CorePac is the boot master. Note that Figure 9-1 does not include bit 0 of the DEVSTAT contents.
Bit 0 is used to select overall system endianess that is independent of the boot mode.
The boot ROM will continue attempting to boot in this mode until successful or an unrecoverable error
occurs.
The PLL settings are shown at the end of this section, and the PLL set-up details can be found in
Section 11.5.
NOTE
It is important to keep in mind that BOOTMODE[15:0] pins map to DEVSTAT[16:1] bits of
the DEVSTAT register.
Figure 9-1. DEVSTAT Boot Mode Pins ROM Mapping
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12 11 10 9
8
7
65 4 321
Mode
X
X
0 ARMEN SYSEN
SlaveAddr
1
Port
Ref clk
Bar Config
X
Width1
X
X
Mode
Param Index
0
Clear
Wait Width
First Block
Chip Sel
Lane Setup NETCP clk
Ref
clk
Ext Con
ARM PLL
CONFIG
SYS PLL
CONFIG
Bus Addr
X
Port
Csel _{Boot Master} Width0
ARM PLL
CONFIG
SYS PLL
CONFIG
0 0 0 SLEEP
Min
000
I²C SLAVE
Port 0 0 1
PCIe
Min 0 1 0 I²C MASTER
011
SPI
X 100
EMIF
101
NAND
Min 1 1 0 Ethernet
X
X
X
Port
111
UART
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Device Boot and Configuration 159