TCI6630K2L Datasheet, PDF (141/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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XMC ´ 4
ARM CorePac
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
6630
S ^SES
S ^SMS
M
S
MSMC
M
Tracer_
MSMC0-8
DDR3A
From TeraNet_3_B
Bridge_5
Bridge_6
Bridge_7
Bridge_8
From TeraNet_3_A
Bridge_9
Bridge_10
BR_SES_0
BR_SES_1
BR_SES_2
BR_SMS_0
BR_SMS_1
BR_SMS_2
TNet_SES
CPU/1
TNet_SMS
CPU/1
TNet_msmc_sys
CPU/1
To TeraNet_3_A
To TeraNet_3P_A
QM_Second _M
EDMA TC_0 M
CC0 _{TC_1 M}
RAC_0_BE1_LP _M
TNet_3_J
CPU/3
TNet3P_U
CPU/3
MPU_7
TNet_3P_V
CPU/3
S
OSR
S ^PCIe_1
To TeraNet 3_B
To TeraNet_3_A
Bridge_1
Bridge_2
Bridge_3
Figure 8-4. TeraNet 3_C
The following tables list the master and slave end-point connections.
Intersecting cells may contain one of the following:
• Y — There is a connection between this master and that slave.
• - — There is NO connection between this master and that slave.
• n — A numeric value indicates that the path between this master and that slave goes through bridge n.
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System Interconnect 141