TCI6630K2L Datasheet, PDF (32/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
DDR3AD56
DDR3AD57
DDR3AD58
DDR3AD59
DDR3AD60
DDR3AD61
DDR3AD62
DDR3AD63
DDR3ACE0
DDR3ACE1
DDR3ABA0
DDR3ABA1
DDR3ABA2
DDR3AA00
DDR3AA01
DDR3AA02
DDR3AA03
DDR3AA04
DDR3AA05
DDR3AA06
DDR3AA07
DDR3AA08
DDR3AA09
DDR3AA10
DDR3AA11
DDR3AA12
DDR3AA13
DDR3AA14
DDR3AA15
DDR3ACAS
DDR3ARAS
DDR3AWE
DDR3ACKE0
DDR3ACKE1
DDR3ACLKOUTP0
DDR3ACLKOUTN0
DDR3ACLKOUTP1
DDR3ACLKOUTN1
DDR3AODT0
DDR3AODT1
DDR3ARESET
DDR3ARZQ0
DDR3ARZQ1
DDR3ARZQ2
BALL
NO.
E30
E29
F29
D30
C30
D29
B28
A28
A14
A11
E11
F12
E12
C14
D14
A18
E14
C15
A17
D15
B16
B17
D17
B12
B18
C17
B11
E18
E16
A13
B13
D12
E17
F17
A16
A15
B15
B14
A12
F11
E15
F13
F9
F21
TYPE IPD/IPU
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
A
A
A
DESCRIPTION
DDR3A EMIF data bus
DDR3A EMIF chip enable
DDR3A EMIF bank address
DDR3A EMIF address bus
DDR3A EMIF address bus
DDR3A EMIF column address strobe
DDR3A EMIF row address strobe
DDR3A EMIF write enable
DDR3A EMIF clock enable0
DDR3A EMIF clock enable1
DDR3A EMIF output clocks to drive SDRAMs (one clock pair per SDRAM)
DDR3A EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3A reset signal
PTV Compensation Reference Resistor PAD for DDR3A
PTV Compensation Reference Resistor PAD for DDR3A
PTV Compensation Reference Resistor PAD for DDR3A
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