TCI6630K2L Datasheet, PDF (22/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Peripherals
CIC2
480 SPI
Interrupts
ARM INTC
Generic
Interrupt
Controller
400
CPU/6 Clock
GTB Counter Clock
Power On Reset
Global
Time Base
Counter
FIQ, IRQ,
Virtual FIQ,
Virtual IRQ
8 PPIs
64 Bits
Cortex
A15
www.ti.com
VBUSP Interface
VBUSP2AXI
Bridge
16 Software
Generated
Inputs
Figure 5-2. ARM Interrupt Controller for Two Cortex-A15 Processor Cores
5.3.4 Endianess
The ARM CorePac can operate in either little endian or big endian mode. When the ARM CorePac is in
little endian mode and the rest of the system is in big endian mode, the bridges in the ARM CorePac are
responsible for performing the endian conversion.
5.4 CFG Connection
The ARM CorePac has two slave ports. The TCI6630K2L masters cannot access the ARM CorePac
internal memory space.
1. Slave port 0 (TeraNet 3P_A) is a 32 bit wide port used for the ARM Trace module.
2. Slave port 1 (TeraNet 3P_B) is a 32 bit wide port used to access the rest of the system configuration.
5.5 Main TeraNet Connection
There is one master port coming out of the ARM CorePac. The master port is a 256 bit wide port for the
transactions going to the MSMC and DDR_EMIF data spaces.
5.6 Clocking and Reset
5.6.1 Clocking
The Cortex-A15 processor core clocks are sourced from this ARM PLL Controller. The Cortex-A15
processor core clock has a maximum frequency of 1.4 GHz. The ARM CorePac subsytem also uses the
SYSCLK1 clock source from the main PLL which is locally divided (/1, /3 and /6) and provided to certain
sub-modules inside the ARM CorePac. AINTC sub module runs at a frequency of SYSCLK1/6.
5.6.2 Reset
The ARM CorePac does not support local reset. It is reset whenever the device is under reset. In addition,
the interrupt controller (AINTC) can only be reset during POR and RESETFULL. AINTC also resets
whenever device is under reset.
For the complete programming model, refer to the KeyStone II Architecture ARM CorePac User's Guide
(SPRUHJ4).
22
ARM CorePac
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