TCI6630K2L Datasheet, PDF (286/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
11.36.2.1 ICEPick Dynamic Tap Insertion
To include more or fewer secondary TAPS in the scan chain, the debugger must use the ICEPick TAP
router to program the TAPs. At its root, ICEPick is a scan-path linker that lets the debugger selectively
choose which subsystem TAPs are accessible through the device-level debug interface. Each secondary
TAP can be dynamically included in or excluded from the scan path. From external JTAG interface point of
view, secondary TAPS that are not selected appear not to exist.
There are two types of components connected through ICEPick to the external debug interface:
• Legacy JTAG Components — C66x implements a JTAG-compatible port and are directly interfaced
with ICEPick and individually attached to an ICEPick secondary TAP.
• CoreSight Components — The CoreSight components are interfaced with ICEPick through the
CS_DAP module. The CS_DAP is attached to the ICEPick secondary TAP and translates JTAG
transactions into APBv3 transactions.
Table 11-68 shows the ICEPick secondary taps in the system. For more details on the test related P1500
TAPs, see the DFTSS specification.
Table 11-68. ICEPick Debug Secondary TAPs
TAP #
0
1
2
3
4
9..13
14
TYPE NAME
n/a n/a
ACCESS IN
IR SCAN SECURE
LENGTH DEVICE
n/a
No
JTAG C66x CorePac0 38
No
JTAG C66x CorePac1 38
No
JTAG C66x CorePac2 38
No
JTAG C66x CorePac3 38
No
JTAG Reserved
NA
No
CS CS_DAP (APB- 4
No
AP)
CS_DAP (AHB-
AP)
DESCRIPTION
Reserved (This is an internal TAP and not exposed at the DEBUGSS
boundary)
C66x CorePac0
C66x CorePac1
C66x CorePac2
C66x CorePac3
Spare ports for future expansion
ARM A15 Cores (This is an internal TAP and not exposed at the
DEBUGSS boundary)
PDSP Cores (This is an internal TAP and not exposed at the DEBUGSS
boundary)
For more information on ICEPick, see the KeyStone II Architecture Debug and Trace User’s Guide
(SPRUHM4).
11.37 Debug Port (EMUx)
The device also supports 34 emulation pins — EMU[33:0], which includes 19 dedicated EMU pins and 15
pins multiplexed with GPIO. These pins are shared by DSP/STM trace, cross triggering, and debug boot
modes as shown in Table 11-72. The 34-pin dedicated emulation interface is also defined in the following
table.
NOTE
Note that if EMU[1:0] signals are shared for cross-triggering purposes in the board level, they
SHOULD NOT be used for trace purposes.
286 TCI6630K2L Peripheral Information and Electrical Specifications
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