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TCI6630K2L Datasheet, PDF (188/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 9-33. LRESETNMI PIN Status Register Field Descriptions (continued)
Bit Field
8
NMI0
7-4 Reserved
3
LR3
2
LR2
1
LR1
0
LR0
Description
C66x CorePac0 in NMI
Reserved
C66x CorePac3 in Local Reset
C66x CorePac2 in Local Reset
C66x CorePac1 in Local Reset
C66x CorePac0 in Local Reset
9.2.3.7 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register clears the status of LRESET and NMI based on CORESEL[2:0].
The LRESETNMI PIN Status Clear Register is shown in the figure and table below.
Figure 9-18. LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
12
Reserved
R-0
Legend: R = Read only; -n = value after reset
11
NMI3
R-0
10
NMI2
R-0
9
NMI1
R-0
8
NMI0
R-0
7
4
Reserved
R-0
3
2
1
0
LR3 LR2 LR1 LR0
R-0 R-0 R-0 R-0
Bit
31-12
11
10
9
8
7-4
3
2
1
0
Field
Reserved
NMI3
NMI2
NMI1
NMI0
Reserved
LR3
LR2
LR1
LR0
Table 9-34. LRESETNMI PIN Status Clear Register Field Descriptions
Description
Reserved
C66x CorePac3 in NMI Clear
C66x CorePac2 in NMI Clear
C66x CorePac1 in NMI Clear
C66x CorePac0 in NMI Clear
Reserved
C66x CorePac3 in Local Reset Clear
C66x CorePac2 in Local Reset Clear
C66x CorePac1 in Local Reset Clear
C66x CorePac0 in Local Reset Clear
9.2.3.8 Reset Status (RESET_STAT) Register
The Reset Status Register (RESET_STAT) captures the status of local reset (LRx) for each of the cores
and also the global device reset (GR). Software can use this information to take different device
initialization steps.
• In case of local reset: The LRx bits are written as 1 and the GR bit is written as 0 only when the C66x
CorePac receives a local reset without receiving a global reset.
• In case of global reset: The LRx bits are written as 0 and the GR bit is written as 1 only when a
global reset is asserted.
The Reset Status Register is shown in the figure and table below.
Figure 9-19. Reset Status Register (RESET_STAT)
31 30
GR
R-1
Legend: R = Read only; -n = value after reset
Reserved
R- 0
4
3
2
1
0
LR3
LR2
LR1
LR0
R-0
R-0
R-0
R-0
188 Device Boot and Configuration
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