TCI6630K2L Datasheet, PDF (212/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
10 Device Operating Conditions
10.1 Absolute Maximum Ratings⁽¹⁾
Over Operating Case Temperature Range (Unless Otherwise Noted)
CVDD
-0.3 V to 1.3 V
CVDD1
-0.3 V to 1.3 V
DVDDR
-0.3 V to 1.98 V
DVDD18
-0.3 V to 2.45 V
DVDD33
-0.3 V to 3.63 V
DDR3AVREFSSTL
0.49 × DVDDR to 0.51 × DVDDR
Supply voltage range⁽²⁾:
VDDAHV
VDDALV
-0.3 V to 1.98 V
-0.3 V to 0.935 V
VDDUSB
-0.3V to 0.935 V
AVDDA1, AVDDA2, AVDDA3,AVDDA4,
AVDDA5
-0.3 V to 1.98 V
AVDDA6, AVDDA7
AVDDA8, AVDDA9, AVDDA10
-0.3 V to 1.98 V
VSS Ground
0V
LVCMOS (1.8 V)
-0.3 V to DVDD18+0.3 V
Input voltage (V_I) range⁽³⁾:
DDR3A
I²C
LVDS
-0.3 V to 1.98 V
-0.3 V to 2.45 V
-0.3 V to DVDD18+0.3 V
LJCB
-0.3 V to 1.3 V
Output voltage (V_O) range⁽³⁾:
SerDes
LVCMOS (1.8 V)
DDR3A
I²C
-0.3 V to VDDAHV1+0.3 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 1.98 V
-0.3 V to 2.45 V
SerDes
-0.3 V to VDDAHV+0.3 V
Operating case temperature range, T_C:
ESD stress voltage, V_ESD(4)
Overshoot/undershoot ⁽⁷⁾
Commercial
Extended
HBM (human body model)⁽⁵⁾
CDM (charged device model)⁽⁶⁾
LVCMOS (1.8 V)
DDR3A
I²C
0°C to 85°C
-40°C to 100°C
±1000 V
±250 V
20% overshoot/undershoot for 20% of
signal duty cycle
Storage temperature range, T_stg:
-65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to V_SS.
(3) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB
Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
(4) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(5) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows
safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary
precautions are taken. Pins listed as 1000 V may actually have higher performance.
(6) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
(7) Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS
signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be V_SS - 0.20 × DVDD18
212 Device Operating Conditions
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