TCI6630K2L Datasheet, PDF (155/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 8-7. Configuration Space Interconnect - Section 3 (continued)
SLAVES
MASTERS
EDMA0_TC1_WR
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
EDMA2_TC0_RD
EDMA2_TC0_WR
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
FFTC_0
FFTC_1
MSMC_SYS
NETCP
PCIe_0_1
QM_Master1
QM_Master2
QM_SEC
RAC_0_BE0
RAC_0_BE1
TAC_FEI_0
USB
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12 12 12 12 - 12 12 12 12 - - - 12 12 12 12 12 12
12 12 12 12 - 12 12 12 12 - - - 12 12 12 12 12 12
- - - - - - - - - 13 13 - - - - - - -
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- - - - - - - - - - - 14 - - - - - -
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12 12 12 12 - 12 12 12 12 - - - 12 12 12 12 12 12
12 12 12 12 - 12 12 12 12 - - - 12 12 12 12 12 12
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12 12 12 12 - 12 12 12 12 - - - 12 12 12 12 12 12
12 12 12 12 - 12 12 12 12 - - - 12 12 12 12 12 12
- - - - - - - - - 13 13 - - - - - - -
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12 12 12 12 - 12 12 12 12 - - - 12 12 12 12 12 12
12 12 12 12 - 12 12 12 12 - - - 12 12 12 12 12 12
- - - - - - - - - - - 14 - - - - - -
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12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
YYYYYYYYYYYYYYYYYY
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12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
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- - - - - - - 12 - - - - - - 12 - - -
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- - - - - - - 12 - 12 12 12 - - - - - -
8.4 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User-programmable
priority registers allow software configuration of the data traffic through the TeraNet. Note that a lower
number means higher priority — PRI = 000b = urgent, PRI = 111b = low.
All other masters provide their priority directly and do not need a default priority setting. Examples include
the C66x CorePacs, whose priorities are set through software in the UMC control registers. All the Packet
DMA-based peripherals also have internal registers to define the priority level of their initiated
transactions.
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