TCI6630K2L Datasheet, PDF (217/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
The clock input buffers for SYSCLK, ARMCLK, ALTCORECLK, DDR3ACLK, NETCPCLK, and SGMIICLK
use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance
state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could
cause damage to the device. Once CVDD is valid, it is acceptable that the P and N legs of these clocks
may be held in a static state (either high and low or low and high) until a valid clock frequency is needed
at that input. To avoid internal oscillation, the clock inputs should be removed from the high impedance
state shortly after CVDD is present.
If a clock input is not used, it must be held in a static state. To accomplish this, the N leg should be pulled
to ground through a 1-kΩ resistor. The P leg should be tied to CVDD to ensure it will not have any voltage
present until CVDD is active. Connections to the IO cells powered by DVDD18 and DVDDR are not
failsafe and should not be driven high before these voltages are active. Driving these IO cells high before
DVDD18 or DVDDR are valid could cause damage to the device.
The device initialization is divided into two phases. The first phase consists of the time period from the
activation of the first power supply until the point at which all supplies are active and at a valid voltage
level. Either of the sequencing scenarios described above can be implemented during this phase. The
figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence.
POR must be held low for the entire power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of
RESETFULL triggers the end of the initialization phase, but both must be inactive for the initialization to
complete. POR must always go inactive before RESETFULL goes inactive as described below. SYSCLK1
in the following section refers to the clock that is used by the CorePacs. See Figure 11-8 for more details.
11.2.1.1 Core-Before-IO Power Sequencing
The details of the Core-before-IO power sequencing are defined in Table 11-2. Figure 11-1 shows power
sequencing and reset control of the TCI6630K2L. POR may be removed after the power has been stable
for the required 100 µsec. RESETFULL must be held low for a period (see item 9 in Figure 11-1) after the
rising edge of POR, but may be held low for longer periods if necessary. The configuration bits shared
with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold
times specified. SYSCLK1 must always be active before POR can be removed.
NOTE
TI recommends a maximum of 80 ms between one power rail being valid and the next power
rail in the sequence starting to ramp.
ITEM
1
2a
Table 11-2. Core-Before-IO Power Sequencing
SYSTEM STATE
Begin Power Stabilization Phase
• CVDD (core AVS) ramps up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous
reset (created from POR) is put into the reset state.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• CVDD1 (core constant) ramps at the same time or within 80 ms of CVDD. Although ramping CVDD1 simultaneously with
CVDD is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as
this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit
cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the
order of twice the specified draw of CVDD1.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• The timing for CVDD1 is based on CVDD valid. CVDD1 and DVDD18/ADDAVH/AVDDAx may be enabled at the same time
but do not need to ramp simultaneously. CVDD1 may be valid before or after DVDD18/ADDAVH/AVDDAx are valid, as long
as the timing above is met.
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