TCI6630K2L Datasheet, PDF (290/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
• Generate a processor debug request
• Generate an interrupt request
• Start/Stop processor trace
• Start/Stop CBA transaction tracing through CPTracers
• Start external logic analyzer trace
• Stop external logic analyzer trace
Table 11-72. Cross-Triggering Connection
NAME
Device-to-device trigger via EMU0/1 pins
MIPI-STM
CT-TBR
CS-TPIU
DSPSS
CP_Tracers
ARM
SOURCE
TRIGGERS
SINK
TRIGGERS
Inside DEBUGSS
YES
YES
NO
YES
YES
YES
NO
YES
Outside DEBUGSS
YES
YES
YES
YES
YES
YES
COMMENTS
This is fixed (not affected by configuration)
Trigger input only for MIPI-STM in DebugSS
DEBUGSS CT-TBR
DEBUGSS CS-TPIU
ARM Cores, ARM CS-STM and ARM CT-
TBR
The following table describes the crosstrigger connection between various cross trigger sources and TI
XTRIG module.
Table 11-73. TI XTRIG Assignment
NAME
C66x CorePac0-3
CPTracer 0..31 (The CPTracer number refers to the SID[4:0] as shown in
Table 11-70
ASSIGNED XTRIG CHANNEL NUMBER
XTRIG 0-3
XTRIG 8 .. 39
11.37.4 Peripherals-Related Debug Requirement
Table 11-74 lists all the peripherals on this device, and the status of whether or not it supports emulation
suspend or emulation request events.
The DEBUGSS supports upto 32 debug suspend sources (processor cores) and 64 debug suspend sinks
(peripherals). The assignment of processor cores is shown in and the assignment of peripherals is shown
in Table 11-74. By default the logical AND of all the processor cores is routed to the peripherals. It is
possible to select an individual core to be routed to the peripheral (For example: used in tightly coupled
peripherals like timers), a logical AND of all cores (Global peripherals) or a logical OR of all cores by
programming the DEBUGSS.DRM module.
The SOFT bit should be programmed based on whether or not an immediate pause of the peripheral
function is required or if the peripheral suspend should occur only after a particular completion point is
reached in the normal peripheral operation. The FREE bit should be programmed to enable or disable the
emulation suspend functionality.
PERIPHERAL
Table 11-74. Peripherals Emulation Support
STOP-
MODE
EMULATION SUSPEND SUPPORT
REAL-TIME
MODE
FREE BIT
Infrastructure Peripherals
STOP BIT
EMULATION
REQUEST
SUPPORT
(cemudbg/emudbg)
DEBUG
PERIPHERAL
ASSIGNMENT
290 TCI6630K2L Peripheral Information and Electrical Specifications
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