TCI6630K2L Datasheet, PDF (246/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 11-27. Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
Bit
31-7
6
5-4
3-0
Field
Reserved
ENSAT
Reserved
BWADJ[11:8]
Description
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
11.5.5 ARM PLL
The ARM PLL generates interface clock for the ARM CorePac. When coming out of power-on reset, ARM
PLL is programmed to a valid frequency during the boot configuration process before being enabled and
used. ARM PLL power is supplied via the ARM PLL power-supply pin (AVDDA1-AVDDA5). An external
EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II
Devices application report (SPRABV0) for detailed recommendations.
SYSCLK(N|P)
DDR3CLK
ALTCORECLK(N|P)
CORECLKSEL[1:0]
PLLM
ARM PLL
PLLD
VCO
0
CLKOD
1
INTBYPASS
ARM
PLLOUT
0
1
BYPASS
Figure 11-21. ARM PLL Block Diagram
ARM
COREPACS
11.5.5.1 ARM PLL Control Registers
The ARM PLL uses two chip-level registers (ARMPLLCTL0 and ARMPLLCTL1) without using the Main
PLL Controller like other PLLs for its configuration. These MMRs (memory-mapped registers) exist inside
the Bootcfg space. To write to these registers, software must go through an un-locking sequence using
the KICK0 and KICK1 registers. These registers reset only on a POR reset.
For valid configurable values of the ARMPLLCTL registers, see Section 9.1.4.1. See Section 9.2.3.5 for
the address location of the KICK registers and their locking and unlocking sequences.
See Figure 11-22 and Table 11-28 for ARMPLLCTL0 details and Figure 11-23 and Table 11-29 for
ARMPLLCTL1 details.
Figure 11-22. ARM PLL Control Register 0 (ARMPLLCTL0)⁽¹⁾
31
24
BWADJ[7:0]
23
BYPASS
22
19
18
CLKOD
PLLM
6
5
0
PLLD
RW-0000 1001
RW-1
Legend: RW = Read/Write; -n = value after reset
RW-0001
RW-0000000010011
RW-000000
(1) This register is Reset on POR only. See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide (SPRUGV2).
Bit Field
31-24 BWADJ[7:0]
23
BYPASS
Table 11-28. ARM PLL Control Register 0 Field Descriptions
Description
BWADJ[11:8] and BWADJ[7:0] are located in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should
be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1.
PLL bypass mode:
• 0 = PLL is not in BYPASS mode
• 1 = PLL is in BYPASS mode
246 TCI6630K2L Peripheral Information and Electrical Specifications
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