TCI6630K2L Datasheet, PDF (158/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 9-2. ARM Boot RAM Memory Map (continued)
START ADDRESS SIZE
0x0c1d_0600
0x99e0
0x0c1d_9fe0
0x2020
0x0c1d_c000
0x180
0x0c1d_c180
0x80
0x0c1d_c200
0x100
0x0c1d_c300
0x100
0x0c1d_c400
0x100
0x0c1d_c500
0x100
0x0c1d_c600
0x99e0
0x0c1d_cfe0
0x2020
0xc0c1e_0000
0x4000
0xc0c1e_4000
0x2ab0
0xc0c1e_6ab0
0x1550
0xc0c1e_8000
0x4000
0xc0c1e_c000
0x2ab0
0xc0c1e_eab0
0x1550
DESCRIPTION
ARM0 Local core Boot data
ARM0 Boot Trace data
ARM1 ⁽¹⁾ Version info
ARM1 Boot progress stack
ARM1 Boot stats
ARM1 Boot Log data
ARM1 RAM Call tables
RAM1 Boot Parameter tables
ARM1 Local core Boot data
ARM1 Boot Trace data
ARM0 Secure Load data
ARM0 Secure Boot data
ARM0 Secure Stack
ARM1 Secure Load data
ARM1 Secure Boot data
ARM1 Secure Stack
(1) The addresses shown for core 1 are the physical addresses. Boot ROM enables the non-secure MMU during the boot process, and the
physical memory shown for ARM core 1(non-secure area) is mapped to the same virtual addresses used by core 0. Core 0 has a flat
map. Likewise for the secure MMU in the secure memory region. When the non-secure boot ROM exits normally the non-secure MMU
is disabled, and for non-secure devices the secure MMU is disabled as well.
9.1.2 Boot Modes Supported
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes
are software-driven, using the BOOTMODE[15:0] device configuration inputs to determine the software
configuration that must be completed. From a hardware perspective, there are four possible boot modes:
• Public ROM Boot when the C6xx CorePac0 is the boot master — The C66x CorePac is released
from reset and begins executing from the L3 ROM base address. The ARM CorePac is also released
from reset at the same time as the C66xCorePac. Both the C66x CorePac and the ARM CorePac read
the bootmode register inside the bootCFG module to determine which is the boot master.
After the Boot ROM for the Cortex-A15 processor reads the bootmode to determine that the C66x
CorePac is the boot master, all Cortex-A15 processors stay idle by executing WFI instruction and
waiting for the C66x CorePac’s interrupt. The chip Boot ROM reads the bootmode register to
determine that the C66x CorePac0 is the boot master, then the C66x CorePac0 performs the boot
process and the other C66x CorePacs execute an IDLE instruction. After the boot process is
completed, the C66x CorePac0 begins to execute the code downloaded during the boot process. If the
downloaded code included code for the other C66x cores and/or the Cortex-A15 processor cores, the
downloaded code may contain logic to write the code execution addresses to the boot address register
for the core that is to execute it. The C66x CorePac0 can then generate an interrupt to the core
causing it to execute the code. When they receive the IPC interrupt, the rest of the C66x CorePacs
and the ARM CorePac complete boot management operations and begin executing from the
predefined location in memory.
• Public ROM Boot when the ARM CorePac Core0 is the boot master — The only difference
between this boot mode and when the C66x CorePac is the boot master, is that the ARM CorePac
performs the boot process while the C66x CorePacs execute idle instructions. When the ARM CorePac
Core0 finishes the boot process, it may send interrupts to the C66x CorePacs and Cortex-A15
processor cores through IPC registers. The C66x CorePacs complete the boot management
operations and begin executing from the predefined locations.
158 Device Boot and Configuration
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