TCI6630K2L Datasheet, PDF (173/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 9-20. UART Boot Parameter Table (continued)
BYTE
OFFSET
44
46
48
50
52
NAME
Flow Control
Data Rate MSW
Data Rate LSW
Blob Base, MSW
Blob Base, LSW
DESCRIPTION
Bits 00 Flow Control
• 0 = No Flow Control
• 1 = RTS_CTS flow control
Bits 15 - 01 Reserved
Baud Rate, MSW
Baud Rate, LSW
For blob format, base address, MSW
For blob format, base address, LSW
CONFIGURED THROUGH
BOOT CONFIGURATION
PINS
NO
NO
NO
NO
NO
9.1.2.4.7 NAND Boot Parameter Table
Table 9-21. NAND Boot Parameter Table
BYTE OFFSET NAME
22
Options
24
numColumnAddrBytes
26
numRowAddrBytes
28
numofDataBytesperPage_msw
30
numofDataBytesperPage_lsw
32
numPagesperBlock
34
busWidth
36
numSpareBytesperPage
38
csel
40
First Block
DESCRIPTION
Bits 00 Geometry
• 0 = Geometry is taken from this table
• 1 = Geometry is queried from NAND device.
Bits 01 Clear NAND
• 0 = NAND Device is a non clear NAND and
requires ECC
• 1 = NAND is a clear NAND and doesn.t need
ECC.
Bits 15 - 02 Reserved
Number of bytes used to specify column address
Number of bytes used to specify row address.
Number of data bytes in each page, MSW
Number of data bytes in each page, LSW
Number of Pages per Block
EMIF bus width. Only 8 or 16 bits is supported.
Number of spare bytes allocated per page.
Chip Select number (valid chip selects are 2-5)
First block for RBL to try to read.
CONFIGURED THROUGH
BOOT CONFIGURATION PINS
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
9.1.2.4.8 DDR3 Configuration Table
The RBL also provides an option to configure the DDR table before loading the image into the external
memory. More information on how to configure the DDR3, refer to the Bootloader User Guide. The
configuration table for DDR3 is shown in Table 9-22
BYTE
OFFSET
0
4
8
12
16
NAME
configselect msw
configselect slsw
configselect lsw
pllprediv
pllMult
Table 9-22. DDR3 Boot Parameter Table
DESCRIPTION
Selecting the configuration register below that to be set. Each
filed below is represented by one bit each.
Selecting the configuration register below that to be set. Each
filed below is represented by one bit each.
Selecting the configuration register below that to be set. Each
filed below is represented by one bit each.
PLL pre divider value (Should be the exact value not value -1)
PLL Multiplier value (Should be the exact value not value -1)
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
NO
NO
NO
NO
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