TCI6630K2L Datasheet, PDF (12/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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4 C66x CorePac
The C66x CorePac consists of several components:
• Level-one and level-two memories (L1P, L1D, L2)
• Data Trace Formatter (DTF)
• Embedded Trace Buffer (ETB)
• Interrupt controller
• Power-down controller
• External memory controller
• Extended memory controller
• A dedicated local power/sleep controller (LPSC)
The C66x CorePac also provides support for big and little endianness, memory protection, and bandwidth
management (for resources local to the CorePac). Figure 4-1 shows a block diagram of the C66x
CorePac.
32KB L1P
Boot
Controller
PLLC
LPSC
GPSC
Memory Controller (PMC) With
Memory Protect/Bandwidth Mgmt
C66x DSP Core
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
In-Circuit Emulation
Instruction Decode
Data Path A
Data Path B
A Register File
A31-A16
A15-A0
B Register File
B31-B16
B15-B0
.M1
.L1 .S1 xx .D1
xx
.M2
.D2 xx .S2 .L2
xx
L2 Cache/
SRAM
1024KB
MSM
SRAM
2048KB
DDR3
SRAM
DMA Switch
Fabric
RSA
RSA
Data Memory Controller (DMC) With
Memory Protect/Bandwidth Mgmt
CFG Switch
Fabric
TCI6630
32KB L1D
Figure 4-1. C66x CorePac Block Diagram
For more detailed information on the C66x CorePac in the TCI6630K2L device, see theTMS320C66x DSP
CorePac User's Guide (SPRUGW0).
12
C66x CorePac
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