TCI6630K2L Datasheet, PDF (3/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

www.ti.com
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
TI's new C66x core launches a new era of DSP technology by combining fixed-point and floating-point
computational capability in the processor without sacrificing speed, size, or power consumption. The raw
computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz
operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The
C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented
(VPi) processing. These enhancements yield tremendous performance improvements in multi-antenna
4.8G signal processing for algorithms like MIMO and beamforming.
The TCI6630K2L contains many wireless basestation coprocessors to offload the bulk of the processing
demands of layer 1 and layer 2 basestation processing. This keeps the cores free for receiver algorithms
and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the
FFTC and TCP3d. A key coprocessor for enabling high data rates is the Bit Rate Coprocessor (BCP),
which handles the entire downlink bit-processing chain and much of the receive bit processing. The
architectural elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any
CPU intervention or overhead, allowing the system to make optimal use of its resources.
TI's scalable multicore SoC architecture solutions provide developers with a range of software-compatible
and hardware-compatible devices to minimize development time and maximize reuse across all
basestation platforms from Femto to Macro.
The TCI6630K2L device has a complete set of development tools that includes: a C compiler, an
assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for
visibility into source code execution.
1.5 Enhancements in KeyStone II
The KeyStone II architecture provides many major enhancements over the previous KeyStone I
generation of devices. The KeyStone II architecture integrates an ARM Cortex-A15 processor quad-core
cluster to enable Layer 2 (MAC/RLC) and higher layer processing.A Digital Front End (DFE) and IQN
subsystem have been added to help meet the more stringent power, size and bill of materials (BOM) cost
requirements of small cell wireless base stations. MSMC internal memory bandwidth is quadrupled with
MSMC V2 architecture improvements. Multicore Navigator supports 8K queues, descriptors and packet
DMA, 4× the number of micro RISC engines and a significant increase in the number of push/pops per
second, compared to the previous generation. The new peripherals that have been added include the
USB 2.0/3.0 controller, USIM interface controller, and Asynchronous EMIF controller for NAND/NOR
memory access. The 2-port Gigabit Ethernet switch in KeyStone I has been replaced with a 4-port Gigabit
Ethernet switch in KeyStone II. Time synchronization support has been enhanced to reduce software
workload and support additional standards like IEEE1588 Annex D/E and SyncE. The number of GPIOs
and serial interface peripherals like I²C and SPI have been increased to enable more board-level control
functionality.
Copyright © 2013–2015, Texas Instruments Incorporated
TCI6630K2L Features and Description
3
Submit Documentation Feedback
Product Folder Links: TCI6630K2L