TCI6630K2L Datasheet, PDF (248/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 11-30. Main PLL Controller/ARM/DFE/PCIe/Shared SerDes/USB/TSREF Clock Input Timing
Requirements⁽¹⁾ (continued)
(see Figure 11-24 through Figure 11-27)
NO.
MIN
MAX
2
tw(ALTCORECLKN)
Pulse width ALTCORECLKN low
0.45*tc(ALTCORECLKN) 0.55*tc(ALTCORECLKN)
2
tw(ALTCORECLKP)
Pulse width ALTCORECLKP high
0.45*tc(ALTCORECLKP) 0.55*tc(ALTCORECLKP)
3
tw(ALTCORECLKP)
Pulse width ALTCORECLKP low
0.45*tc(ALTCORECLKP) 0.55*tc(ALTCORECLKP)
4
tr(ALTCORECLK_200 mV) Transition time ALTCORECLK differential rise
time (200 mV)
50
350
4
tf(ALTCORECLK_200 mV) Transition time ALTCORECLK differential fall
time (200 mV)
50
350
5
tj(ALTCORECLKN)
Jitter, peak_to_peak _ periodic ALTCORECLKN
100
5
tj(ALTCORECLKP)
Jitter, peak_to_peak _ periodic ALTCORECLKP
100
SGMIICLK[P:N]
1
tc(SGMIICLKN)
Cycle time SGMIICLKN cycle time
6.4
1
tc(SGMIICLKP)
Cycle time SGMIICLKP cycle time
6.4
3
tw(SGMIICLKN)
Pulse width SGMIICLKN high
0.45*tc(SGMIICLKN)
0.55*tc(SGMIICLKN)
2
tw(SGMIICLKN)
Pulse width SGMIICLKN low
0.45*tc(SGMIICLKN)
0.55*tc(SGMIICLKN)
2
tw(SGMIICLKP)
Pulse width SGMIICLKP high
0.45*tc(SGMIICLKP)
0.55*tc(SGMIICLKP)
3
tw(SGMIICLKP)
Pulse width SGMIICLKP low
0.45*tc(SGMIICLKP)
0.55*tc(SGMIICLKP)
4
tr(SGMIICLK_250mV)
Transition time SGMIICLK differential rise time
(250 mV)
50
350
4
tf(SGMIICLK_250mV)
Transition time SGMIICLK differential fall time
(250 mV)
50
350
5
tj(SGMIICLKN)
Jitter, RMS SGMIICLKN
8
5
tj(SGMIICLKP)
Jitter, RMS SGMIICLKP
8
PCIECLK[P:N]
1
tc(PCIECLKN)
Cycle time PCIECLKN cycle time
10
1
tc(PCIECLKP)
Cycle time PCIECLKP cycle time
10
3
tw(PCIECLKN)
Pulse width PCIECLKN high
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
2
tw(PCIECLKN)
Pulse width PCIECLKN low
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
2
tw(PCIECLKP)
Pulse width PCIECLKP high
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
3
tw(PCIECLKP)
Pulse width PCIECLKP low
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
4
tr(PCIECLK[P:N])
Rise time PCIECLK[P:N] differential rise time
(10% to 90%)
0.2*tc(PCIECLK[P:N])
4
tf(PCIECLK[P:N])
Fall time PCIECLK[P:N] differential fall time (10%
to 90%)
0.2*tc(PCIECLK[P:N])
5
tj(PCIECLKN)
Jitter, RMS PCIECLKN
4
5
tj(PCIECLKP)
Jitter, RMS PCIECLKP
4
SHARED_SERDES_0_REFCLK[P:N]
1
tc(SHARED_SERDES_0_ Cycle time SHARED_SERDES_0_REFCLKN
REFCLKN)
cycle time
8.138
1
tc(SHARED_SERDES_0_ Cycle time SHARED_SERDES_0_REFCLKP
REFCLKP)
cycle time
8.138
3
tw(SHARED_SERDES_0_ Pulse width SHARED_SERDES_0_REFCLKN
0.45*tc(SHARED_
0.55*tc(SHARED_
REFCLKN)
high
SERDES_0_REFCLKN) SERDES_0_REFCLKN)
2
tw(SHARED_SERDES_0_ Pulse width SHARED_SERDES_0_REFCLKN
0.45*tc(SHARED_
0.55*tc(SHARED_
REFCLKN)
low
SERDES_0_REFCLKN) SERDES_0_REFCLKN)
2
tw(SHARED_SERDES_0_ Pulse width SHARED_SERDES_0_REFCLKP
0.45*tc(SHARED_
0.55*tc(SHARED_
REFCLKP)
high
SERDES_0_REFCLKP) SERDES_0_REFCLKP)
3
tw(SHARED_SERDES_0_ Pulse width SHARED_SERDES_0_REFCLKP
0.45*tc(SHARED_
0.55*tc(SHARED_
REFCLKP)
low
SERDES_0_REFCLKP) SERDES_0_REFCLKP)
4
tr(SHARED_SERDES_0_ Rise time SHARED_SERDES_0_REFCLK[P:N]
REFCLK[P:N])
differential rise time (10% to 90%)
0.2*tc(SHARED_SERDES
_0_REFCLK[P:N])
4
tf(SHARED_SERDES_0_ Fall time SHARED_SERDES_0_REFCLK[P:N]
REFCLK[P:N])
differential fall time (10% to 90%)
0.2*tc(SHARED_SERDES
_0_REFCLK[P:N])
5
tj(SHARED_SERDES_0_ Jitter, RMS SHARED_SERDES_0_REFCLKN
REFCLKN)
4
UNIT
ns
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ps
ps
ps, RMS
ps, RMS
ns
ns
ns
ns
ns
ns
ps
ps
ps, RMS
ps, RMS
ns
ns
ns
ns
ns
ns
ps
ps
ps, RMS
248 TCI6630K2L Peripheral Information and Electrical Specifications
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