TCI6630K2L Datasheet, PDF (288/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
EMU
PINS
EMU14
EMU13
EMU12
EMU11
EMU10
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
EMU3
EMU2
EMU1
EMU0
Table 11-69. Emulation Interface with Different Debug Port Configurations (continued)
CROSS
TRIGGERING
Trigger1
Trigger0
ARM TRACE
TRCDTa[10] TRCDTb[12]
TRCDTa[9] TRCDTb[11]
TRCDTa[8] TRCDTb[10]
TRCDTa[7] TRCDTb[9]
TRCDTa[6] TRCDTb[8]
TRCDTa[5] TRCDTb[7]
TRCDTa[4] TRCDTb[6]
TRCDTa[3] TRCDTb[5]
TRCDTa[2] TRCDTb[4]
TRCDTa[1] TRCDTb[3]
TRCDTa[0] TRCDTb[2]
TRCCTRL TRCCTRL
TRCCLK
TRCCLK
TRCDTb[1]
TRCDTb[0]
DSP TRACE
TRCDTa[10] TRCDTb[12]
TRCDTa[9] TRCDTb[11]
TRCDTa[8] TRCDTb[10]
TRCDTa[7] TRCDTb[9]
TRCDTa[6] TRCDTb[8]
TRCDTa[5] TRCDTb[7]
TRCDTa[4] TRCDTb[6]
TRCDTa[3] TRCDTb[5]
TRCDTa[2] TRCDTb[4]
TRCDTa[1] TRCDTb[3]
TRCDTa[0] TRCDTb[2]
TRCCLKB TRCCLKB
TRCCLKA TRCCLKA
TRCDTb[1]
TRCDTb[0]
STM
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
DEBUG BOOT
MODE
dbgbootmode[1]
dbgbootmode[0]
11.37.1 Concurrent Use of Debug Port
The following combinations are possible concurrently:
• Trigger 0/1
• Trigger 0/1 and STM Trace (up to 4 data pins)
• Trigger 0/1 and STM Trace (up to 4 data pins) and C66x Trace (up to 20 data pins)
• Trigger 0/1 and STM Trace (1-4 data pins) and ARM Trace (27-24 data pins)
• STM Trace (1-4 data pins) and ARM Trace (29-26 data pins)
• Trigger 0/1 and ARM Trace (up to 29 data pins)
• ARM Trace (up to 32 data pins)
288 TCI6630K2L Peripheral Information and Electrical Specifications
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