TCI6630K2L Datasheet, PDF (231/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their
normal operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device,
including the reset-isolated logic, when the device is already powered up. For this reason, the
RESETFULL pin, unlike POR, should be driven by the on-board host control other than the power good
circuitry. For power-on reset, the Core PLL Controller comes up in bypass mode and the PLL is not
enabled. Other resets do not affect the state of the PLL or the dividers in the PLL Controller.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR and
RESETFULL pins asserted (driven low). While POR is asserted, all pins except RESETSTAT will be
set to high-impedance. After the POR pin is deasserted (driven high), all Z group pins, low group pins,
and high group pins are set to their reset state and remain in their reset state until otherwise
configured by their respective peripheral. All peripherals that are power-managed are disabled after a
power-on reset and must be enabled through the Device State Control Registers (for more details, see
Section 9.2.3).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT is driven low, indicating that the device is in
reset.
3. POR must be held active until all supplies on the board are stable, and then for at least an additional
period of time (as specified in Section 11.2.1) for the chip-level PLLs to lock.
4. The POR pin can now be de-asserted.Reset-sampled pin values are latched at this point. Then, all
chip-level PLLs are taken out of reset, locking sequences begin, and all power-on device initialization
processes begin.
5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time,
the DDR3A PLL has completed its locking sequences and are supplying a valid clock. The system
clocks of the PLL controllers are allowed to finish their current cycles and then are paused for 10
cycles of their respective system reference clocks. After the pause, the system clocks are restarted at
their default divide-by settings.
6. The device is now out of reset and code execution begins as dictated by the selected boot mode.
NOTE
To most of the device, reset is de-asserted only when the POR and RESET pins are both
de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is
held low past the low period of the POR pin, most of the device will remain in reset. The
RESET pin should not be tied to the POR pin.
11.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test logic, emulation logic, and reset-
isolated modules. POR should also remain de-asserted during this time.
Hard reset is initiated by the following:
• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
• Emulation
By default, all the initiators listed above are configured to generate a hard reset. Except for emulation, all
of the other three initiators can be configured in the RSCFG Register in the PLL Controller to generate soft
resets.
The following sequence must be followed during a hard reset:
1. The RESET pin is asserted (driven low) for a minimum of 24 CLKIN1 cycles. During this time, the
RESET signal propagates to all modules (except those specifically mentioned above). To prevent off-
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TCI6630K2L Peripheral Information and Electrical Specifications 231
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