TCI6630K2L Datasheet, PDF (163/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
9.1.2.2.3 SPI Boot Device Configuration
16
Width1
15 14
Mode
Figure 9-5. SPI Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
13 12
11
10
9
8
7
65 4 321
0
Param ldx/Offset
Csel
Boot Master
Width0 Port Min
011
Lendian
Bit
16-7
Field
Width1:Width0
15-14 Mode
13-12
11-9
Csel
Param Idx/Offset
8
Boot Master
7
Width0
6-5
Port
4
Min
3-1
Boot Devices
0
Lendian
Table 9-7. SPI Device Configuration Field Descriptions
Description
SPI address width configuration
• 00 = 16-bit address values are used
• 01 = 24-bit address values are used (default)
• 01 = 32-bit address values are used
• 11 = 32-bit address values are used
Clk Polarity/ Phase
• 0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
• 1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling
edges. Input data is latched on the rising edge of SPICLK.
• 2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge (default).
• 3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising
edges. Input data is latched on the falling edge of SPICLK.
The chip select field value 0-3 (default = 0)
Parameter Table Index: 0-7
This value specifies the parameter table index when the C66x is the boot master
This value specifies the start read address at 8K times this value when the ARM is the boot master
Boot Master select
• 0 = ARM is boot master (default)
• 1 = C66x is boot master
Width0
Specify SPI port
• 0 = SPI0 used (default)
• 1 = SPI1 used
• 2 = SPI2 used
• 3 = Reserved
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field
Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1]
• 011 = SPI boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
9.1.2.2.4 EMIF Boot Device Configuration
16
15
14
Base Addr Wait Width
Figure 9-6. EMIF Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
13
12
11 10 9
8
765 4
Chip Sel
ARM PLL Cfg Boot Master=0 Sys PLL Cfg Min
321
100
0
Lendian
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Device Boot and Configuration 163