TCI6630K2L Datasheet, PDF (256/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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Table 11-37. DFE PLL Control Register 1 Field Descriptions (DFEPLLCTL1)
Bit
31-15
14
Field
Reserved
PLLRST
13
DFEPLL
12-7
6
5-4
3-0
Reserved
ENSAT
Reserved
BWADJ[11:8]
Description
Reserved
PLL Reset bit
• 0 = PLL Reset is released
• 1 = PLL Reset is asserted
• 0 = Not supported
• 1 = DFEPLL
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in DFEPLLCTL0 and DFEPLLCTL1 registers. BWADJ[11:0] should
be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1.
11.8.2 DFE Clock Divider Control Register (DFE_CLKDIV_CTL)
The DFE_CLKDIV_CTL register is used to program the clock divider that exists at the chip level, it divides
down the output of the clock signal from the DFE PLL Controller and is routed to the DFE subsytem core
logic.
Figure 11-38. DFE Clock Divider Control Register (DFE_CLKDIV_CTL)
31
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
1
0
DIV_MODE
RW-00
Bit
31-2
1-0
Field
Reserved
DIV_MODE
Table 11-38. DFE Clock Divider Control Register Field Descriptions
Description
A 2-bit field that selects the values for the reference divider
• 00 = DFE PLL output clock divided by 4 (default)
• 01 = DFE PLL output clock divided by 2
• 10 = DFE PLL output clock divided by2
• 11 = Reserved
11.8.3 DFE Clock Sync Control Register (DFE_CLKSYNC_CTL)
The DFE_CLKSYNC_CTL register is used to enable the SYSCLK and SYSREF synchronization logic.
Synchronous Ethernet (SyncE) allows distribution of traceable frequency synchronization to packet nodes
the need to communication with TDM network elements. It is also used to distribute timing to applications
that rely on precise frequency synchronization such as wireless backhaul.
In TCI6630K2L, SyncE is achieved by deriving a TSRXCLKOUTn clock signal based on recovered RX
clock from the SGMII SerDes interface. The TSRXCLKOUTn is fed into an DPLL which will supply, along
with a clock generator, TSREFCLK, SGMII, SYSCLK, and SYSREF clocks. SyncE may also be achieved
by software PLL, via reading registers from CPTS, then drive a clock adjusting signal via SPI (similar to
IEEE 1588 clock adjusting method).
Figure 11-39. DFE Clock Sync Control Register (DFE_CLKSYNC_CTL)
31
Legend: RW = Read/Write; - n = value after reset
Reserved
R-0
1
0
SYNC_EN
RW-0
256 TCI6630K2L Peripheral Information and Electrical Specifications
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