TCI6630K2L Datasheet, PDF (239/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
11.5.2.5 Main PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device power-up. The device should not be taken out of reset until this stabilization
time has elapsed.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in
order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the
Main PLL reset time value, see Table 11-14.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset to when the PLL
Controller can be switched to PLL mode. The Main PLL lock time is given in Table 11-14.
Table 11-14. Main PLL Stabilization, Lock, and Reset Times
PLL stabilization time
PLL lock time
PLL reset time
PARAMETER
MIN
TYP
100
1000
(1) C = SYSCLK1(N|P) cycle time in ns.
MAX
2000 × C⁽¹⁾
UNIT
µs
ns
11.5.3 PLL Controller Memory Map
The memory map of the Main PLL Controller is shown in Table 11-15. TCI6630K2L-specific Main PLL
Controller Register definitions can be found in the sections following Table 11-15. For other registers in
the table, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide (SPRUGV2).
It is recommended to use read-modify-write sequence to make any changes to the valid bits in the Main
PLL Controller registers.
Note that only registers documented here are accessible on the TCI6630K2L. Other addresses in the
Main PLL Controller memory map including the Reserved registers must not be modified. Furthermore,
only the bits within the registers described here are supported.
Table 11-15. PLL Controller Registers (Including Reset Controller)
HEX ADDRESS RANGE
00 0231 0000 - 00 0231 00E3
00 0231 00E4
00 0231 00E8
00 0231 00EC
00 0231 00F0
00 0231 00F0 - 00 0231 00FF
00 0231 0100
00 0231 0104
00 0231 0108
00 0231 010C
00 0231 0110
00 0231 0114
00 0231 0118
00 0231 011C
00 0231 0120
00 0231 0124
00 0231 0128
00 0231 012C - 00 0231 0134
00 0231 0138
ACRONYM
-
RSTYPE
RSTCTRL
RSTCFG
RSISO
-
PLLCTL
-
SECCTL
-
PLLM
-
PLLDIV1
PLLDIV2
PLLDIV3
-
POSTDIV
-
PLLCMD
REGISTER NAME
Reserved
Reset Type Status Register (Reset Main PLL Controller)
Software Reset Control Register (Reset Main PLL Controller)
Reset Configuration Register (Reset Main PLL Controller)
Reset Isolation Register (Reset Main PLL Controller)
Reserved
PLL Control Register
Reserved
PLL Secondary Control Register
Reserved
PLL Multiplier Control Register
Reserved
PLL Controller Divider 1Register
PLL Controller Divider 2 Register
PLL Controller Divider 3Register
Reserved
PLL Controller Post-Divide Register
Reserved
PLL Controller Command Register
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TCI6630K2L Peripheral Information and Electrical Specifications 239
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