TCI6630K2L Datasheet, PDF (197/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Figure 9-37. Timer Output Selection1 Register (TOUTPSEL1)
31
30 29
24 23
22 21
16 15
14 13
87
65
0
Reserved
TOUTPSEL7
Reserved
TOUTPSEL5
Reserved
TOUTPSEL4
Reserved
TOUTPSEL3
R-0
RW-010001
R-0
RW-010000
R-0
RW-010101
R-0
RW-010100
Legend: R = Read only; RW = Read/Write; -n = value after reset
Bit
31-30
23-22
15-14
7-6
29-24
21-16
13-8
5-0
Field
Reserved
TOUTPSELx
Table 9-48. Timer Output Selection Field Description
Description
Reserved
Output select for TIMO[x]
• 000000: TOUTL0
• 000001: TOUTH0
• 000010: TOUTL1
• 000011: TOUTH1
• 000100: TOUTL2
• 000101: TOUTH2
• 000110: TOUTL3
• 000111: TOUTH3
• 001000: reserved
• 001001: reserved
• 001010: reserved
• 001011: reserved
• 001100: reserved
• 001101: reserved
• 001110: reserved
• 001111: reserved
• 010000: TOUTL8
• 010001: TOUTH8
• 010010: TOUTL9
• 010011: TOUTH9
• 010100: TOUTL10
• 010101: TOUTH10
• 010110: TOUTL11
• 010111: TOUTH11
• 011000: TOUTL12
• 011001: TOUTH12
• 011010: TOUTL13
• 011011: TOUTH13
• 011100: TOUTL14
• 011101: TOUTH14
• 011110: TOUTL15
• 011111: TOUTH15
• 110000: TOUTL8
• 110001: TOUTH8
• 110010: TOUTL9
• 110011: TOUTH9
• 110100: reserved
• 110101: reserved
• 110110: reserved
• 110111: reserved
• 111000: reserved
• 111001: reserved
• 111010: reserved
• 111011: reserved
• 111100: reserved
• 111101: reserved
• 111110: reserved
• 111111: reserved
9.2.3.21 Reset Mux (RSTMUXx) Register
Software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through
RSTMUX3 for each of the C66x CorePacs and RSTMUX8 and RSTMUX9 for the ARM CorePac on the
device. These registers are located in Bootcfg memory space. The Reset Mux Register is shown in the
figure and table below.
Figure 9-38. Reset Mux Register
31
10
9
8
7
5
4
Reserved
EVTSTATCLR Reserved
DELAY
EVTSTAT
R-0000 0000 0000 0000 0000 00
RC-0
R-0
RW-100
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
3
1
OMODE
RW-000
0
LOCK
RW-0
Table 9-49. Reset Mux Register 0..3 (RSTMUX0-RSTMUX3) Field Descriptions
Bit
31-10
9
Field
Reserved
EVTSTATCLR
8
Reserved
Description
Reserved
Clear event status
• 0 = Writing 0 has no effect
• 1 = Writing 1 to this bit clears the EVTSTAT bit
Reserved
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Device Boot and Configuration 197