TCI6630K2L Datasheet, PDF (4/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
1.6 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
Memory Subsystem
TCI6630K2L
72-Bit
DDR3 EMIF
Debug & Trace
Boot ROM
Semaphore
Power
Management
PLL
5´
2MB
MSM
SRAM
MSMC
RRRSRSASASAA
RRRSRSASASAA
CCCCCCoCoC6o6ro6r66er6er6ex6PexPxP™xP™a™a™acaccc
3P3P2-3P2C-3PK2C-K2Ca-KBCaKBcaBcaLhBcLhc1eLh1eLh1e1e _{D3D32D-32CD-3K2C-K2Ca-KBCaKBcaBcaLhBcLhc1eLh1eLh1e1e}
11010120204242K4K4KBKBBLBL2L2L2C2CCaCacacahchcehehee
32KB L1 32KB L1
P-Cache D-Cache
ARM
A15
1MB L2 Cache
ARM
A15
32KB L1 32KB L1
P-Cache D-Cache
OSR
1MB
4´
EDMA
3´
4 C66x DSP Cores @ up to 1.2 GHz
2 ARM Cores @ up to 1.2 GHz
TeraNet
Coprocessors
RAC
TAC
VCP2
4´
TCP3d
2´
FFTC
2´
BCP
Multicore Navigator
Queue Packet
Manager DMA
IQNet
DFE
5-Port
Ethernet
Switch
Security
Accelerator
Packet
Accelerator
Network
Coprocessor
Figure 1-1. Functional Block Diagram
Table of Contents
1 TCI6630K2L Features and Description .............. 1
1.1 Features .............................................. 1
1.2 Applications........................................... 2
1.3 KeyStone Architecture................................ 2
1.4 Device Description ................................... 2
1.5 Enhancements in KeyStone II........................ 3
1.6 Functional Block Diagram ............................ 4
2 Revision History ......................................... 6
3 Device Characteristics.................................. 7
3.1 C66x DSP CorePac .................................. 8
3.2 ARM CorePac ........................................ 8
3.3 Development Tools ................................... 9
3.4 Device Nomenclature................................. 9
3.5 Related Documentation from Texas Instruments ... 10
3.6 Community Resources .............................. 11
3.7 Trademarks.......................................... 11
3.8 Electrostatic Discharge Caution..................... 11
3.9 Glossary ............................................. 11
4 C66x CorePac ........................................... 12
4.1 Memory Architecture ................................ 13
4.2 Memory Protection .................................. 16
4.3 Bandwidth Management ............................ 17
4
Table of Contents
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