TCI6630K2L Datasheet, PDF (8/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 3-1. Characteristics of the TCI6630K2L Processor (continued)
Frequency
Voltage
BGA Package
Process Technology
Product Status⁽³⁾
HARDWARE FEATURES
DSP
ARM
Core (V)
I/O (V)
25 mm × 25 mm
µ;m
Product Preview (PP), Advance Information (AI), or
Production Data (PD)
TCI6630K2L
1.0 GHz
1.2 GHz
1.0 GHz
1.2 GHz
SmartReflex variable supply
.85 V, 1.0 V, 1.8 V and 3.3 V
900-Pin Flip-Chip Plastic BGA (CMS)
0.028 µm
PD
(3) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
3.1 C66x DSP CorePac
The C66x DSP CorePac extends the performance of the C64x+ and C674x CPUs through enhancements
and new features. Many of the new features target increased performance for vector processing. The
C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-
bit data. On the C66x DSP, the vector processing capability is improved by extending the width of the
SIMD instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. The C66x CPU
also supports SIMD for floating-point operations. Improved vector processing capability (each instruction
can process multiple data in parallel) combined with the natural instruction level parallelism of C6000™
architecture (e.g., execution of up to 8 instructions per cycle) results in a very high level of parallelism that
can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler.
Each C66x DSP CorePac has two Rake and Search Accelerators (RSA) integrated on-chip. The tightly
coupled accelerator RSA can be used for:
• Chip rate spreading of WCDMA Rel’99, CDMA2000, HSDPA, and HSDPA+
• Chip rate despreading and correlation of WCDMA Rel’99, HSDPA, and HSDPA+ (e.g., Rake receiver,
preamble detection)
• Reed-Muller decoding
For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see
the following documents:
• TMS320C66x DSP CPU and Instruction Set Reference Guide (SPRUGH7)
• TMS320C66x DSP Cache User's Guide (SPRUGY8)
• TMS320C66x DSP CorePac User's Guide (SPRUGW0)
3.2 ARM CorePac
The ARM CorePac of the TCI6630K2L integrates a Cortex-A15 Cluster (4 Cortex-A15 processors) with
additional logic for bus protocol conversion, emulation, interrupt handling, and debug related
enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order, superscalar
pipeline with integrated L1 caches. The implementation also supports advanced SIMDV2 (Neon
technology) and VFPv4 (Vector Floating Point) architecture extensions, security, virtualization, LPAE
(Large Physical Address Extension), and multiprocessing extensions. The quad core cluster includes a
4MB L2 cache and support for AMBA4 AXI and AXI Coherence Extension (ACE) protocols.
8
Device Characteristics
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