TCI6630K2L Datasheet, PDF (164/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Bit
Field
16
Base Addr
15
Wait
14
Width
13-12 Chip Sel
8
Boot Master
7-5
SYS PLL Setting
4
Min
3-1
Boot Devices
0
Lendian
Table 9-8. EMIF Boot Device Configuration Field Descriptions
Description
Base address (0-3) used to calculate the branch address. Branch address is the chip select plus Base
Address *16MB
Extended Wait
• 0 = Extended Wait disabled
• 1 = Extended Wait enabled
EMIF Width
• 0 = 8-bit EMIF Width
• 1 = 16-bit EMIF Width
Chip Sel specifies the chip select region, EMIF16 CS2-EMIF16 CS5.
• 00 = EMIF16 CS2( EMIFCE0 )
• 01 = EMIF16 CS3 ( EMIFCE1 )
• 10 = EMIF16 CS4 ( EMIFCE2 )
• 11 = EMIF16 CS5 ( EMIFCE3 )
Boot Master select
• 0 = ARM is boot master
• 1 = C66x is boot master
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock
setting for the device. Table 9-23 shows settings for various input clock frequencies.
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field
Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1] used in conjunction with Boot Device [4]
• 100 = EMIF boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
9.1.2.2.5 NAND Boot Device Configuration
16
Clear
15
14
First Block
Figure 9-7. NAND Boot Device Configuration Fields
13
12
Chip Sel
DEVSTAT Boot Mode Pins ROM Mapping
11
10
9
8
7
6
5
ARM PLL Cfg
Boot
Master
Sys PLL Cfg
4321
Min
101
0
Lendian
Bit
Field
16
Clear
15-14 First Block
13-12 Chip Sel
Table 9-9. NAND Boot Device Configuration Field Descriptions
Description
ClearNAND
• 0 = Device is not a ClearNAND (default)
• 1 = Device is a ClearNAND
First Block. This value is used to calculate the first block read. The first block read is the first block value
*16.
Chip Sel specifies the chip select region, EMIF16 CS2-EMIF16 CS5.
• 00 = EMIF16 CS2( EMIFCE0 )
• 01 = EMIF16 CS3 ( EMIFCE1 )
• 10 = EMIF16 CS4 ( EMIFCE2 )
• 11 = EMIF16 CS5 ( EMIFCE3 )
164 Device Boot and Configuration
Submit Documentation Feedback
Product Folder Links: TCI6630K2L
Copyright © 2013–2015, Texas Instruments Incorporated