TCI6630K2L Datasheet, PDF (5/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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4.4 Power-Down Control ................................ 17
4.5 C66x CorePac Revision............................. 18
4.6 C66x CorePac Register Descriptions ............... 18
5 ARM CorePac ........................................... 19
5.1 Features ............................................. 20
5.2 System Integration .................................. 20
5.3 ARM Cortex-A15 Processor......................... 20
5.4 CFG Connection .................................... 22
5.5 Main TeraNet Connection........................... 22
5.6 Clocking and Reset ................................. 22
6 Terminals ................................................ 23
6.1 Package Terminals.................................. 23
6.2 Pin Map ............................................. 23
6.3 Terminal Functions.................................. 28
6.4 Pullup/Pulldown Resistors .......................... 58
7 Memory, Interrupts, and EDMA for TCI6630K2L . 59
7.1 Memory Map Summary for TCI6630K2L ........... 59
7.2 Memory Protection Unit (MPU)...................... 69
7.3 Interrupts for TCI6630K2L........................... 83
7.4 Enhanced Direct Memory Access (EDMA3)
Controllerfor TCI6630K2L.......................... 130
8 System Interconnect ................................. 137
8.1 Internal Buses and Switch Fabrics ................ 137
8.2 Switch Fabric Connections Matrix - Data Space .. 137
8.3 TeraNet Switch Fabric Connections Matrix -
Configuration Space ............................... 148
8.4 Bus Priorities....................................... 155
9 Device Boot and Configuration .................... 157
9.1 Device Boot ........................................ 157
9.2 Device Configuration............................... 176
10 Device Operating Conditions ...................... 212
10.1 Absolute Maximum Ratings........................ 212
10.2 Recommended Operating Conditions ............. 213
10.3 Electrical Characteristics........................... 214
10.4 Power Supply to Peripheral I/O Mapping .......... 215
11 TCI6630K2L Peripheral Information and
Electrical Specifications............................. 216
11.1 Recommended Clock and Control Signal Transition
Behavior............................................ 216
11.2 Power Supplies .................................... 216
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
11.3 Power Sleep Controller (PSC) ..................... 223
11.4 Reset Controller.................................... 230
11.5 PLLs................................................ 234
11.6 DDR3A PLL ........................................ 251
11.7 NETCP PLL ........................................ 253
11.8 DFE PLL ........................................... 254
11.9 External Interrupts ................................. 259
11.10 On-Chip Standalone RAM (OSR) ................ 259
11.11 DDR3A Memory Controller ....................... 259
11.12 I²C Peripheral..................................... 261
11.13 SPI Peripheral .................................... 265
11.14 UART Peripheral ................................. 268
11.15 PCIe Peripheral................................... 269
11.16 Packet Accelerator ............................... 269
11.17 Security Accelerator .............................. 270
11.18 Network Coprocessor Gigabit Ethernet (GbE)
Switch Subsystem ................................. 270
11.19 SGMII Management Data Input/Output (MDIO) . 272
11.20 Timers............................................. 273
11.21 Rake Search Accelerator (RSA).................. 274
11.22 Enhanced Viterbi-Decoder Coprocessor (VCP2) 274
11.23 Turbo Decoder Coprocessor (TCP3d)............ 274
11.24 Turbo Encoder Coprocessor (TCP3e)............ 274
11.25 Bit Rate Coprocessor (BCP)...................... 274
11.26 General-Purpose Input/Output (GPIO) ........... 275
11.27 Semaphore2 ...................................... 277
11.28 IQNet (IQN)....................................... 277
11.29 Digital Front End (DFE)........................... 279
11.30 Receive Accelerator Coprocessor (RAC) ........ 280
11.31 Transmit Accelerator Coprocessor (TAC) ........ 280
11.32 Fast Fourier Transform Coprocessor (FFTC) .... 280
11.33 Universal Serial Bus 3.0 (USB 3.0)............... 280
11.34 Universal Subscriber Identity Module (USIM) .... 280
11.35 EMIF16 Peripheral................................ 281
11.36 Emulation Features and Capability ............... 283
11.37 Debug Port (EMUx)............................... 286
12 Mechanical Data ...................................... 295
12.1 Thermal Data ...................................... 295
12.2 Packaging Information ............................. 295
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