TCI6630K2L Datasheet, PDF (148/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
8.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
The figures below show the connections between masters and slaves through various sections of the
TeraNet.
Bridge_12
Bridge_13
From TeraNet_3_A
Bridge_14
From TeraNet_3_C
CorePac_0 _M
CorePac_1 _M
CorePac_2 _M
CorePac_3 _M
K2L
MPU_2
Tracer_QM_CFG1
Tracer_QM_CFG2
Tracer_SM
MPU_6
MPU_10
MPU_4
Tracer_
RAC_CFG_1
TNet_3P_H
CPU/3
S MPU (´ 15)
M
QM_SS_
CFG1
M
QM_SS_
CFG2
S ^Semaphore
S ^RAC_0_CFG
Tracer
_EDMA
CC0 & CC4
TNet_3P_M
CPU/3
Tracer
_EDMA
CC1 - CC3
TNet_3P_C
CPU/3
MPU_9
TNet_3P_L
CPU/3
Tracer_INTC
MPU_0
Tracer_CFG
S
CC0
S ^{TC (´ 2)}
S
CC1
S ^{TC (´ 4)}
S
CC2
S ^{TC (´ 4)}
S ^{ARM INTC}
S ^CP_INTC0/2
TETB
CorePac (´ 4)
DBG_TBR_SYS
(Debug_SS)
TBR_SYS_
ARM_CorePac
To TeraNet_3P_B
To TeraNet_3P_Tracer
Figure 8-5. TeraNet 3P_A
148 System Interconnect
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