TCI6630K2L Datasheet, PDF (131/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
• 64 DMA channels for all EDMA3CC
– Manually triggered (CPU writes to channel controller register)
– External event triggered
– Chain triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels per EDMA3CCx
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• Two transfer controllers and two event queues with programmable system-level priority for
EDMA3CC0, EDMA3CC3 and EDMA3CC4
• Four transfer controllers and four event queues with programmable system-level priority for each of
EDMA3CC1 and EDMA3CC2
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
7.4.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode.
Constant addressing mode is applicable to a very limited set of use cases. For most applications
increment mode can be used. On the TCI6630K2L SoC, the EDMA can use constant addressing mode
only with the enhanced Viterbi decoder coprocessor (VCP) and the enhanced turbo decoder coprocessor
(TCP). Constant addressing mode is not supported by any other peripheral or internal memory in the DSP.
Note that increment mode is supported by all peripherals, including VCP and TCP.For more information
on these two addressing modes, see the KeyStone Architecture Enhanced Direct Memory Access 3
(EDMA3) User's Guide (SPRUGS5).
For the range of memory addresses that includes EDMA3 channel controller (EDMA3CC) control registers
and EDMA3 transfer controller (TPTC) control registers, see Section Section 7.1. For memory offsets and
other details on EDMA3CC and TPTC Control Register entries, see the KeyStone Architecture Enhanced
Direct Memory Access 3 (EDMA3) User's Guide (SPRUGS5).
7.4.2 EDMA3 Channel Controller Configuration
Table 7-30 shows the configuration for each of the EDMA3 channel controllers present on the device.
Table 7-30. EDMA3 Channel Controller Configuration
DESCRIPTION
Number of DMA channels in channel controller
Number of QDMA channels
Number of interrupt channels
Number of PaRAM set entries
Number of event queues
Number of transfer controllers
Memory protection existence
Number of memory protection and shadow regions
EDMA3 CC0
64
8
64
512
2
2
Yes
8
EDMA3 CC1
64
8
64
512
4
4
Yes
8
EDMA3 CC2
64
8
64
512
4
4
Yes
8
7.4.3 EDMA3 Transfer Controller Configuration
Each transfer controller on the device is designed differently based on considerations like performance
requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The
parameters that determine the transfer controller configurations are:
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Memory, Interrupts, and EDMA for TCI6630K2L 131
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