TCI6630K2L Datasheet, PDF (293/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
For more information on the AET, see the following documents:
• Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
(SPRA753)
• Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report (SPRA387)
11.37.6 Trace
The device supports trace. Trace is a debug technology that provides a detailed, historical account of
application code execution, timing, and data accesses. Trace collects, compresses, and exports debug
information for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for trace advanced emulation, see the Emulation and
Trace Headers Technical Reference Manual (SPRU655).
11.37.6.1 Trace Electrical Data/Timing
Table 11-77. Trace Switching Characteristics
(see Figure 11-69)
NO.
PARAMETER
MIN
1
t_w(DPnH)
Pulse duration, DPn/EMUn high
2.4
1
t_w(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh
1.5
2
t_w(DPnL)
Pulse duration, DPn/EMUn low
2.4
2
t_w(DPnL)10% Pulse duration, DPn/EMUn low detected at 10% Voh
1.5
3
t_sko(DPn)
Output skew time, time delay difference between DPn/EMUn pins
configured as trace
-1
t_skp(DPn)
Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-
high (tplh) propagation delays.
t_{sldp_o}(DPn) Output slew rate DPn/EMUn
3.3
MAX
1
UNIT
ns
ns
ns
ns
ns
600 ps
V/ns
Buffer Buffers
DP[n] /
Inputs
EMU[n] Pins
B
A
C
A
T_PLH
B
C
T_PLH
1
2
3
Figure 11-69. Trace Timing
11.37.7 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) interface is used to support boundary scan and emulation of the
device. The boundary scan supported allows for an asynchronous test reset (TRST) and only the five
baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device
follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes (SGMII) support the
AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain
fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant
with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit
Specification (EAI/JESD8-5).
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TCI6630K2L Peripheral Information and Electrical Specifications 293
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