TCI6630K2L Datasheet, PDF (108/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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EVENT NO.
465
466
467
468
469
470
471
472
473
474
Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NAME
GPIO_INT35
GPIO_INT36
GPIO_INT37
GPIO_INT38
GPIO_INT39
NETCP_SWITCH_STAT_INT2
NETCP_SWITCH_STAT_INT3
PCIE_1_INT7
PCIE_1_INT12
PCIE_1_INT13
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
NetCP interrupt
NetCP interrupt
PCIe_1 interrupt
PCIe_1 interrupt
PCIe_1 interrupt
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC0, EDMACC1 and EDMA3CC2)
EVENT NO.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
EVENT NAME
GPIO_INT8
GPIO_INT9
GPIO_INT10
GPIO_INT11
GPIO_INT12
GPIO_INT13
GPIO_INT14
GPIO_INT15
DBGTBR_DMAINT
Reserved
Reserved
TETB_FULLINT0
TETB_HFULLINT0
TETB_ACQINT0
TETB_FULLINT1
TETB_HFULLINT1
TETB_ACQINT1
TETB_FULLINT2
TETB_HFULLINT2
TETB_ACQINT2
TETB_FULLINT3
TETB_HFULLINT3
TETB_ACQINT3
Reserved
QMSS_INTD_1_HIGH_16
QMSS_INTD_1_HIGH_17
QMSS_INTD_1_HIGH_18
QMSS_INTD_1_HIGH_19
QMSS_INTD_1_HIGH_20
QMSS_INTD_1_HIGH_21
QMSS_INTD_1_HIGH_22
QMSS_INTD_1_HIGH_23
QMSS_INTD_1_HIGH_24
QMSS_INTD_1_HIGH_25
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Debug trace buffer (TBR) DMA event
TETB0 is full
TETB0 is half full
TETB0 acquisition has been completed
TETB1 is full
TETB1 is half full
TETB1 acquisition has been completed
TETB2 is full
TETB2 is half full
TETB2 acquisition has been completed
TETB3 is full
TETB3 is half full
TETB3 acquisition has been completed
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
108 Memory, Interrupts, and EDMA for TCI6630K2L
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