TCI6630K2L Datasheet, PDF (166/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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9.1.2.3 Ethernet (SGMII) Boot Device Configuration
16
Lane
Setup
15
14
NetCP Ref
clk Clock
Figure 9-8. Ethernet (SGMII) Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
13 12 11 10 9
8
765
4 321
Ext Con
ARM PLL Cfg
Boot Master
Sys PLL Cfg Min
110
0
Lendian
Bit
16
15
14
13-12
11-9
8
7-5
4
3-1
0
Table 9-10. Ethernet (SGMII) Boot Device Configuration Field Descriptions
Field
Lane Setup
NetCP clk
Ref Clock
Ext Con
Lane Setup/ARM PLL
Setting
Description
Lane Setup.
• 0 = All SGMII ports enabled (default)
• 1 = Only SGMII port 0 enabled
NETCP clock reference
• 0 = NETCP clocked at the same reference as the core reference
• 1 = NETCP clocked at the same reference as the 125 Mhz SerDes reference clock (default)
NETCP SerDes reference clock frequency
• 0 = 125MHz (default)
• 1 = 156.25MHz
External connection mode
• 0 = MAC to MAC connection, master with auto negotiation
• 1 = MAC to MAC connection, slave with auto negotiation (default)
• 2 = MAC to MAC, forced link, maximum speed
• 3 = MAC to fiber connection
When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default
settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the
device. Table 9-23 shows settings for various input clock frequencies.
Boot Master
SYS PLL Setting
Min
When Boot Master =1 (C66x is Boot Master), pin [10:9] are used as Lane Set up.
• 0 = All SGMII ports enabled (default)
• 1 = Only SGMII port 0 enabled
• 2 = SGMII port 0 and 1 enabled
• 3 = SGMII port 0, 1 and 2 enabled
• 4-7 = Reserved
Boot Master select
• 0 = ARM is boot master (default)
• 1 = C66x is boot master
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock
setting for the device. Default system reference clock is 156.25 MHz. Table 9-23 shows settings for
various input clock frequencies. (default = 4)
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field
Descriptions table for configuration bits with a "(default)" tag added in the description column).
Boot Devices
Lendian
When Min = 0, all fields must be independently configured.
Boot Devices
• 110 = Ethernet boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
166 Device Boot and Configuration
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