TCI6630K2L Datasheet, PDF (215/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
10.4 Power Supply to Peripheral I/O Mapping
Table 10-1. Power Supply to Peripheral I/O Mapping⁽¹⁾⁽²⁾
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
POWER SUPPLY
I/O BUFFER TYPE
ASSOCIATED PERIPHERAL
SYSCLK(P|N) PLL input buffer
LJCB
ALTCORECLK(P|N) PLL input buffer
CVDD
Supply core AVS voltage
DDR3ACLK(P|N) PLL input buffer
LVDS
TSREFCLK(P|N) Input buffer
RP1CLK(P|N) input buffer
VDDALV
LJCB
SERDES low voltage
PCIECLK(P|N) SerDes Clock Reference
VDDAHV
SerDes IO voltage
SerDes/CML
SGMIICLK(P|N) SerDes PLL input buffer
USBCLK(P|M) SerDes Clock Reference
DVDDR
DDR3 supply I/O voltage
DDR3A
All DDR3Amemory controller peripheral I/O buffer
All GPIO peripheral I/O buffer
All JTAG and EMU peripheral I/O buffer
All TIMER peripheral I/O buffer
DVDD18
1.8-V supply I/O voltage
LVCMOS (1.8 V)
All SPI peripheral I/O buffer
All RESETs, NMI, control peripheral I/O buffer
All SmartReflex peripheral I/O buffer
All MDIO peripheral I/O buffer
All UART peripheral I/O buffer
Open-drain (1.8 V) All I²C peripheral I/O buffer
(1) Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to
power peripheral I/O buffers and clock input buffers.
(2) Please see the Hardware Design Guide for KeyStone II Devices application report (SPRABV0) for more information about individual
peripheral I/O.
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Device Operating Conditions 215