TCI6630K2L Datasheet, PDF (19/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
5 ARM CorePac
The ARM CorePac is added in the TCI6630K2L to enable the ability for layer 2 and layer 3 processing on-
chip. Operations such as traffic control, local O&M, NBAP/FP termination, and SCTP processing can all
be performed with the Cortex-A15 processor core.
The ARM CorePac of the TCI6630K2L integrates one or more Cortex-A15 processor clusters with
additional logic for bus protocol conversion, emulation, interrupt handling, and debug related
enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order superscalar
execution engine with integrated L1 caches. The implementation also supports advanced SIMDv2 (NEON
technology) and VFPv4 (vector floating point) architecture extensions, security, virtualization, LPAE (large
physical address extension), and multiprocessing extensions. The ARM CorePac includes a 1MB L2
cache and support for AMBA4 AXI and AXI coherence extension (ACE) protocols. An interrupt controller is
included in the ARM CorePac to handle host interrupt requests in the system.
The ARM CorePac has three functional clock domains, including a high-frequency clock domain used by
the Cortex-A15. The high-frequency domain is isolated from the rest of the device by asynchronous
bridges.
The following figure shows the ARM CorePac.
480 SPI
Interrupts
TeraNet
(CFG)
KeyStone II ARM CorePac (Dual Core)
ARM
ARM INTC
Generic
Interrupt
Controller
400
IRQ,
FIQ,
VIRQ,
VFIQ
8
PPI
VBUSP2AXI
Bridge
64
Global
Bits
Time Base
Counter
ARM Cluster
ARM
A15
32KB L1 32KB L1
P-Cache D-Cache
ARM
A15
32KB L1 32KB L1
P-Cache D-Cache
STM
ATB
ARM
Trace
ATB
PTM (´4)
Debug
CTI/CTM
CTM
CTI (´4)
VBUSP
OCP
ATB
APB ^{APB MUX}
APB
APB
ARM
VBUSP
Registers
VBUSP
AXI-VBUS
Master
256b
VBUSM
Endian
CFG
Boot Config
ARM
CorePac
Clock
Main PLL
ARM
A15 Core
Clock
ARM PLL
PSC
Figure 5-1. ARM CorePac Block Diagram
TeraNet
(DMA)
Debug
SubSystem
TeraNet
(CFG)
MSMC
DDR3
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