TCI6630K2L Datasheet, PDF (129/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 7-28. IPC Generation Registers (IPCGRx) (continued)
ADDRESS START ADDRESS END
0x0262021C
0x0262021F
0x02620220
0x0262023F
0x02620240
0x02620243
0x02620244
0x02620247
0x02620248
0x0262024B
0x0262024C
0x0262024F
0x02620250
0x02620253
0x02620254
0x02620257
0x02620258
0x0262025B
0x0262025C
0x0262025F
0x02620260
0x02620263
0x02620264
0x02620267
0x02620268
0x0262026B
0x0262026C
0x0262026F
0x02620270
0x0262027B
0x0262027C
0x0262027F
0x02620280
0x02620283
0x02620284
0x02620287
0x02620288
0x0262028B
0x0262028C
0x0262028F
0x02620290
0x02620293
0x02620294
0x02620297
0x02620298
0x0262029B
0x0262029C
0x0262029F
0x026202A0
0x026202A3
0x026202A4
0x026202A7
0x026202A8
0x026202AB
0x026202AC
0x026202AF
0x026202B0
0x026202BB
0x026202A0
0x026202BB
0x026202BC
0x026202BF
SIZE
4B
32B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
12B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
12B
28B
4B
REGISTER NAME
Reserved
Reserved
IPCGR0
IPCGR1
IPCGR2
IPCGR3
Reserved
Reserved
Reserved
Reserved
IPCGR8
IPCGR9
Reserved
Reserved
Reserved
IPCGRH
IPCAR0
IPCAR1
IPCAR2
IPCAR3
Reserved
Reserved
Reserved
Reserved
IPCAR8
IPCAR9
Reserved
Reserved
Reserved
Reserved
IPCARH
DESCRIPTION
IPC Generation Register for C66x CorePac0
IPC Generation Register for C66x CorePac1
IPC Generation Register for C66x CorePac2
IPC Generation Register for C66x CorePac3
IPC Generation Register for ARM CorePac0
IPC Generation Register for ARM CorePac1
IPC Generation Register for Host
IPC Acknowledgment Register for C66x CorePac0
IPC Acknowledgment Register for C66x CorePac1
IPC Acknowledgment Register for C66x CorePac2
IPC Acknowledgment Register for C66x CorePac3
IPC Acknowledgment Register for ARM CorePac0
IPC Acknowledgment Register for ARM CorePac1
IPC Acknowledgement Register for host
7.3.4 NMI and LRESET
The Non-Maskable Interrupts (NMI) can be generated by chip-level registers and the LRESET can be
generated by software writing into LPSC registers. LRESET and NMI can also be asserted by device pins
or watchdog timers. One NMI pin and one LRESET pin are shared by all eight C66x CorePacs on the
device. The CORESEL[3:0] pins can be configured to select between the eight C66x CorePacs available
as shown in Table 7-29.
CORESEL[3:0] PIN
INPUT
XXXX
0000
0001
0010
0011
1XXX
LRESET PIN
INPUT
X
0
0
0
0
0
Table 7-29. LRESET and NMI Decoding
NMI PIN
INPUT
X
X
X
X
X
X
LRESETNMIEN PIN
INPUT
1
0
0
0
0
0
RESET MUX BLOCK OUTPUT
No local reset or NMI assertion
Assert local reset to C66x CorePac0
Assert local reset to C66x CorePac1
Assert local reset to C66x CorePac2
Assert local reset to C66x CorePac3
Assert local reset to all C66x CorePacs
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