TCI6630K2L Datasheet, PDF (204/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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Table 9-61. Chip Miscellaneous Control Register (CHIP_MISC_CTL1) Field Descriptions
Bit
31-12
11
Field
Reserved
DDR3A_PSC_LOCK_n
Description
Reserved.
By default this bit is set to 0. In this case it doesn't allow DDR3A to be clock gated and it will always
be in the enabled state. It avoids DDR3A PSC transitioning through its various state-machines.
10-0 Reserved
When this bit is set to 1, the DDR3A PSC is un-locked, thereby allowing DDR3A to be reset
independently of the rest of the device.
9.2.3.30 System Endian Status Register (SYSENDSTAT)
This register provides a way for reading the system endianness in an endian-neutral way. A zero value
indicates big endian and a non-zero value indicates little endian. The SYSENDSTAT register captures the
LENDIAN bootmode pin and is used by the BOOTROM to guide the bootflow. The value is latched on the
rising edge of POR or RESETFULL .
Figure 9-47. System Endian Status Register
31
Reserved
R-0000 0000 0000 0000 0000 0000 0000 000
Legend: RW = Read/Write; -n = value after reset
1
0
SYSENDSTAT
R-0
Bit
31-1
0
Field
Reserved
SYSENDSTAT
Table 9-62. System Endian Status Register Descriptions
Description
Reserved
Reflects the same value as the LENDIAN bit in the DEVSTAT register.
• 0 - C66x/System is in Big Endian
• 1 - C66x/System is in Little Endian
9.2.3.31 PLL Input Clock Selection Status Register (PLLCLKSEL_STAT)
This register provides a way for reading the status of the PLL input clock selection pins. Any time this
register is read, it reflects the status of the clock pin selection.
Figure 9-48. PLL Input Clock Selection Status Register
31
Legend: RW = Read/Write; -n = value after reset
Reserved
R-0
21
0
CORECLKSELSTAT
R-00
Table 9-63. PLL Input Clock Selection Status Register Descriptions
Bit
31-2
1-0
Field
Description
Reserved
Reserved
CORECLKSELSTAT Reflects the status of the clock pin selection:
[1:0]
• 00 - SYSCLK drives the MAIN/ARM/NETCP PLLs (default)
• 01 - ALTCORECLK drives the MAIN/ARM/NETCP PLLs
• 1x - DDR3ACLK drives the MAIN/ARM/NETCP PLLs
9.2.3.32 SYNECLK_PINCTL Register
This register controls the routing of recovered clock signals from any Ethernet port (SGMII/AIL of the
multiport switches) to the clock output TSRXCLKOUT0.
204 Device Boot and Configuration
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