TCI6630K2L Datasheet, PDF (206/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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Table 9-65. USB_PHY_CTL0 Register Field Descriptions (continued)
Bit
Field
Description
6
PHY_TC_TEST_POWERDOWN SS Function Circuits Power-Down Control.
_SSP
Powers down all SS function circuitry in the PHY for IDDQ testing.
5
PHY_TC_TEST_POWERDOWN HS Function Circuits Power-Down Control
_HSP
Powers down all HS function circuitry in the PHY for IDDQ testing.
4
PHY_TC_LOOPBACKENB
Loop-back Test Enable
3
Reserved
2
UTMI_VBAUSVLDEXT
Places the USB3.0 PHY in HS Loop-back mode, which concurrently enables the HS receive
and transmit logic.
• 1 = During HS data transmission, the HS receive logic is enabled.
• 0 = During HS data transmission, the HS receive logic is disabled.
• Reserved
External VBUS Valid Indicator
1
UTMI_TXBITSTUFFENH
Function: Valid in Device mode and only when the VBUSVLDEXTSEL signal is set to 1'b1.
VBUSVLDEXT indicates whether the VBUS signal on the USB cable is valid. In addition,
VBUSVLDEXT enables the pull-up resistor on the D+ line.
• 1 = VBUS signal is valid, and the pull-up resistor on D+ is enabled.
• 0 = VBUS signal is not valid, and the pull-up resistor on D+ is disabled.
High-byte Transmit Bit-Stuffing Enable
0
UTMI_TXBITSTUFFEN
Function: controls bit stuffing on DATAINH[7:0] when OPMODE[1:0]=11b.
• 1 = Bit stuffing is enabled.
• 0 = Bit stuffing is disabled.
Low-byte Transmit Bit-Stuffing Enable
Function: controls bit stuffing on DATAIN[7:0] when OPMODE[1:0]=11b.
• 1 = Bit stuffing is enabled.
• 0 = Bit stuffing is disabled.
Figure 9-51. USB_PHY_CTL1 Register
31
Reserved
R-0
4
3
2
PIPE_TX2RX_LOOPBK
PIPE_EXT_PCLK_REQ PIPE_ALT_CLK_SEL
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
6
5
PIPE_REF_CLKREQ_N
R-0
1
0
PIPE_ALT_CLK_REQ PIPE_ALT_CLK_EN
R-0
R/W-0
Table 9-66. USB_PHY_CTL1 Register Field Descriptions
Bit
31-6
5
Field
Reserved
PIPE_REF_CLKREQ_N
Description
Reserved
Reference Clock Removal Acknowledge.
When the pipeP_power-down control into the PHY turns off the MPLL in the P3 state,
PIPE_REF_CLKREQ_N is asserted after the PLL is stable and the reference clock can be
removed.
4
PIPE_TX2RX_LOOPBK
Loop-back.
When this signal is asserted, data from the transmit predriver is looped back to the receiver
slicers. LOS is bypassed and based on the tx_en input so that rx_los=!tx_data_en.
3
PIPE_EXT_PCLK_REQ
External PIPE Clock Enable Request.
When asserted, this signal enables the pipeP_pclk output regardless of power state (along
with the associated increase in power consumption).
206 Device Boot and Configuration
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