TCI6630K2L Datasheet, PDF (157/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
9 Device Boot and Configuration
9.1 Device Boot
9.1.1 Boot Sequence
The boot sequence is a process by which the internal memory is loaded with program and data sections.
The boot sequence is started automatically after each power-on reset or warm reset.
The TCI6630K2L supports several boot processes that begins execution at the ROM base address, which
contains the bootloader code necessary to support various device boot modes. The boot processes are
software-driven and use the BOOTMODE[15:0] device configuration inputs to determine the software
configuration that must be completed. For more details on boot sequence see the KeyStone II Architecture
ARM Bootloader User's Guide (SPRUHJ3).
For TCI6630K2L non-secure devices, there are two types of booting: the C66x CorePac as the boot
master and the ARM CorePac as the boot master. For secure devices, the C66x CorePac is always the
secure master and the C66x CorePac0 or ARM CorePac Core0 can be the boot master. The ARM
CorePac does not support no-boot mode. Both the C66x CorePacs and the ARM CorePac need to read
the bootmode register to determine how to proceed with the boot.
Table 9-1 shows memory space reserved for boot by the C66x CorePac.
START ADDRESS
0x80_0000
0x8e_7f80
0x8e_8000
0x8e_fe80
0x8e_fff0
0x8f_7800
0x8f_a290
0x8f_e290
0x8f_e320
0x8f_e410
0x8f_e520
0x8f_f91c
0x8f_fd20
0x8f_fea0
0x8f_ff00
0x8f_fff8
0x8f_fffc
Table 9-1. C66x DSP Boot RAM Memory Map
SIZE
0x1_0000
0x80
0x7f00
0x7e80
4
0x410
0x4000
0x90
0x20
0xf0
0x13fc
0x404
0x180
0x60
0x80
0x4
0x4
DESCRIPTION
Reserved
C66x CorePac ROM version string
Ethernet Package memory
PCIe config block
Host Data Address (boot magic address for secure boot through master
peripherals)
Secure host Data structure
Boot Stack
Boot Log Data
Boot Status Stack
Boot Stats
Boot Data
Boot Trace Info
DDR Config
Boot RAM call table
Boot Parameter table
Secure Signal Magic address
Boot Magic address
Table 9-2 shows addresses reserved for boot by the ARM CorePac.
START ADDRESS SIZE
0x0c1d_8000
0x180
0x0c1d_0180
0x80
0x0c1d_0200
0x100
0x0c1d_0300
0x100
0x0c1d_0400
0x100
0x0c1d_0500
0x100
Table 9-2. ARM Boot RAM Memory Map
DESCRIPTION
ARM0 Version info
ARM0 Boot progress stack
ARM0 Boot stats
ARM0 Boot Log data
ARM0 RAM Call tables
RAM0 Boot Parameter tables
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