TCI6630K2L Datasheet, PDF (38/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
SHARED_SERDES_
2_RXN1
SHARED_SERDES_
2_RXP1
SHARED_SERDES_
2_TXN1
SHARED_SERDES_
2_TXP1
SHARED_SERDES_
2_REFRES
BALL
NO.
AK26
AK25
AG24
AG25
AE23
SHARED_SERDES_
0_RXN0
SHARED_SERDES_
0_RXN1
SHARED_SERDES_
0_RXP0
SHARED_SERDES_
0_RXP1
SHARED_SERDES_
0_TXN0
SHARED_SERDES_
0_TXN1
SHARED_SERDES_
0_TXP0
SHARED_SERDES_
0_TXP1
AJ19
AK20
AJ18
AK19
AH17
AG18
AH18
AG19
SHARED_SERDES_
3_RXN0
SHARED_SERDES_
3_RXP0
SHARED_SERDES_
3_TXN0
SHARED_SERDES_
3_TXP0
SHARED_SERDES_
3_RXN1
SHARED_SERDES_
3_RXP1
SHARED_SERDES_
3_TXN1
SHARED_SERDES_
3_TXP1
SHARED_SERDES_
3_REFRES
AJ22
AJ21
AH20
AH21
AK23
AK22
AG21
AG22
AE22
VCL²
VCNTL0
VCNTL1
VCNTL2
VCNTL3
VCNTL4
VCNTL5
VD²
AH27
AJ27
AK28
AJ28
AG27
AH27
AH26
AH26
SPI0CLK
L29
SPI0DIN
N27
TYPE IPD/IPU DESCRIPTION
I
Ethernet MAC SGMII receive data
I
O
Ethernet MAC SGMII transmit data
O
A
SGMII SerDes reference resistor input (3 kΩ ±1%)
AIL/JESD
I
I
CSISC2_0 RX (shared B4 Marco shared between AIL and two JESD)
I
I
O
O
CSISC2_0 TX(shared B4 Marco shared between AIL and two JESD)
O
O
SGMII/PCIe
I
Ethernet MAC SGMII or PCIe receive data
I
O
Ethernet MAC SGMII or PCIe transmit data
O
I
Ethernet MAC SGMII or PCIe receive data
I
O
Ethernet MAC SGMII or PCIe transmit data
O
A
SGMII/PCIe SerDes reference resistor input (3 kΩ ±1%)
IOZ
IOZ
IOZ
OZ
OZ
OZ
OZ
IOZ
IOZ Down
IOZ Down
SmartReflex
Voltage Control I²C Clock(² pin is a secondary function and is shared with VCNTL4)
Voltage Control Outputs to variable core power supply
Voltage Control I²C Data(² pin is a secondary function and is shared with VCNTL5)
SPI0
SPI0 clock
SPI0 data In
38
Terminals
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