TCI6630K2L Datasheet, PDF (211/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Bit
31-21
20
19-13
12-4
3
2-0
Table 9-70. USB_PHY_CTL5 Register Field Descriptions
Field
Reserved
PHY_REF_CLKDIV2
Description
Reserved
Input Reference Clock Divider Control.
If the input reference clock frequency is greater than 100 MHz, this signal must be asserted.
The reference clock frequency is then divided by 2 to keep it in the range required by the
MPLL.
PHY_MPLL_MULTIPLIER[6:0]
When this input is asserted, the ref_ana_usb2_clk (if used) frequency will be the reference
clock frequency divided by 4.
MPLL Frequency Multiplier Control.
PHY_SSC_REF_CLK_SEL
Multiplies the reference clock to a frequency suitable for intended operating speed.
Spread Spectrum Reference Clock Shifting.
Reserved
PHY_SSC_RANGE
Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
corresponds to frequency-synthesis coefficient.
• . ssc_ref_clk_sel[8:6] = modulous - 1
• . ssc_ref_clk_sel[5:0] = 2's complement push amount.
Reserved
Spread Spectrum Clock Range.
Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is
spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator.
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