TCI6630K2L Datasheet, PDF (167/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
9.1.2.3.1 PCIe Boot Device Configuration
16
Ref clk
15 14 13 12
Bar Config
Figure 9-9. PCIe Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
11 10 9
8
765
4
ARM PLL Cfg
Boot Master=0
Sys PLL Cfg
Port
321
001
0
Lendian
Bit
Field
16
Ref clk
15-12 Bar Config
11-9
8
ARM PLL Setting
Boot Master
7-5
SYS PLL Setting
4
Port
3-1
Boot Devices
0
Lendian
Table 9-11. PCIe Boot Device Configuration Field Descriptions
Description
PCIe Reference clock frequency
• 0 = 100MHz
• 1 = Reserved
PCIe BAR registers configuration
This value can range from 0 to 0xf. See Table 9-12.
ARM PLL Setting. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the
maximum clock setting for the device. Table 9-23 shows settings for various input clock frequencies.
Boot Master select
• 0 = ARM is boot master
• 1 = C66x is boot master
The PLL default settings are determined by the [7:5] bits.This will set the PLL to the maximum clock
setting for the device. Default system reference clock is 156.25 MHz. Table 9-23 shows settings for
various input clock frequencies.
Boot configured for boot.
• 0 = Port 0 configured for boot
• 1 = Port 1 configured for boot.
Boot Devices[4:1]
• 001 = PCIe boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
BAR cfg
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
Table 9-12. BAR Config / PCIe Window Sizes
BAR0
PCIe MMRs
BAR1
32
16
16
32
16
16
32
32
64
4
4
4
32-Bit Address Translation
BAR2
BAR3
BAR4
32
32
32
16
32
64
32
32
64
32
32
64
16
64
64
32
64
64
32
64
64
32
64
128
64
128
256
128
128
128
128
128
256
128
256
256
BAR5
Clone of
BAR4
64-Bit Address Translation
BAR2/3
BAR4/5
256
512
1024
2048
256
512
1024
2048
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Device Boot and Configuration 167