TCI6630K2L Datasheet, PDF (238/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 11-13. Main PLL Controller Module Clock Domains Internal and Shared Local Clock
Dividers (continued)
CLOCK
SYSCLK1
SYSCLK1
SYSCLK2
MODULE
INTERNAL CLOCK
DIVIDER(S)
Fast Fourier Transform Coprocessor (FFTC)
/3
Multicore Navigator Queue Manager
/3
MultiCore Shared Memory Controller (MSMC)
/1
PCI express (PCIe)
/2, /3, /4, /6
Receive Accelerator Coprocessor (RAC)
/3, /4
ROM
/6
Serial Gigabit Media Independent Interface (SGMII)
/2, /3, /6, /8
Transmit Accelerator Coprocessor (TAC)
/3
Turbo Decoder Coprocessor (TCP3d)
/2, /3
Universal Asynchronous Receiver/Transmitter (UART)
/6
Universal Serial Bus 3.0 (USB 3.0)
/3, /6
SYSCLK1 Shared Local Clock Dividers
Power/Sleep Controller (PSC)
--
EDMA
Memory Protection Units (MPUx)
--
Semaphore
TeraNet (SYSCLK1/3 domain)
DFE
CSISC2_0
CSISC2_1
Boot Config
General-Purpose Input/Output (GPIO)
I²C
--
Security Manager
Serial Peripheral Interconnect (SPI)
TeraNet (CPU /6 domain)
Timers
SYSCLK2 Internal Clock Dividers
SmartReflex
/12, /128
SHARED LOCAL CLOCK
DIVIDER
--
--
--
--
--
--
--
--
--
--
--
/12, /24
/3
/6
--
11.5.2.3 Module Clock Input
Table 11-7 lists various clock domains in the device and their distribution in each peripheral. The table
also shows the distributed clock division in modules and their mapping with source clocks of the device
PLLs.
11.5.2.4 Main PLL Controller Operating Modes
The Main PLL Controller has two modes of operation: bypass mode and PLL mode. The mode of
operation is determined by the BYPASS bit of the PLL Secondary Control Register (SECCTL).
• In bypass mode, PLL input is fed directly out as SYSCLK1.
• In PLL mode, SYSCLK1 is generated from the PLL output using the values set in the PLLM and PLLD
fields in the MAINPLLCTL0 Register.
External hosts must avoid access attempts to the DSP while the frequency of its internal clocks is
changing. User software must implement a mechanism that causes the DSP to notify the host when the
PLL configuration has completed.
238 TCI6630K2L Peripheral Information and Electrical Specifications
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