TCI6630K2L Datasheet, PDF (132/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
• FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight
data. The data FIFO is where the read return data read by the TC read controller from the source
endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued
by a transfer controller.
• DSTREGDEPTH: This determines the number of destination FIFO register sets. The number of
destination FIFO register sets for a transfer controller determines the maximum number of outstanding
transfer requests.
All four parameters listed above are fixed by the design of the device.
Table 7-31 shows the configuration of each of the EDMA3 transfer controllers present on the device.
Table 7-31. EDMA3 Transfer Controller Configuration
PARAMETER
FIFOSIZE
BUSWIDTH
DSTREGDEPTH
DBS
EDMA3 CC0
TC0
TC1
1024
bytes
1024
bytes
32 bytes 32 bytes
4 entries 4 entries
128 bytes 128
bytes
TC0
1024
bytes
16 bytes
4 entries
128
bytes
EDMA3 CC1
TC1
TC2
1024
bytes
1024
bytes
16 bytes 16 bytes
4 entries 4 entries
128 bytes 128 bytes
TC3
1024
bytes
16 bytes
4 entries
128 bytes
TC0
1024
bytes
16 bytes
4 entries
128 bytes
EDMA3 CC2
TC1
TC2
1024
bytes
1024
bytes
16 bytes 16 bytes
4 entries 4 entries
128
bytes
128 bytes
TC3
1024
bytes
16 bytes
4 entries
128 bytes
7.4.4 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 64 DMA channels for all EDMA3CC that can be used to service system
peripherals and to move data between system memories. DMA channels can be triggered by
synchronization events generated by system peripherals. The following tables list the source of the
synchronization event associated with each of the EDMA3CC DMA channels. On the TCI6630K2L, the
association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured,
processed, prioritized, linked, chained, and cleared, etc., see the KeyStone Architecture Enhanced Direct
Memory Access 3 (EDMA3) User's Guide (SPRUGS5).
EVENT NO.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Table 7-32. EDMA3CC0 Events for TCI6630K2L
EVENT NAME
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
CIC_2_OUT66
CIC_2_OUT67
CIC_2_OUT68
CIC_2_OUT69
CIC_2_OUT70
CIC_2_OUT71
DESCRIPTION
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
132 Memory, Interrupts, and EDMA for TCI6630K2L
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TCI6630K2L