TCI6630K2L Datasheet, PDF (273/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
11.20 Timers
The timers can be used to time events, count events, generate pulses, interrupt the CorePacs, and send
synchronization events to the EDMA3 channel controller.
11.20.1 Timers Device-Specific Information
The TCI6630K2L device has up to twenty 64-bit timers in total, of which Timer0 through Timer3 are
dedicated to each of the four C66x CorePacs as watchdog timers and can also be used as general-
purpose timers. Timer16 and Timer17 are dedicated to each of the Cortex-A15 processor cores as a
watchdog timer and can also be used as general-purpose timers. The remaining timers can be configured
as general-purpose timers only, with each timer programmed as a 64-bit timer or as two separate 32-bit
timers.
When operating in 64-bit mode, the timer counts either module clock cycles or input (TINPLx) pulses
(rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a
software-programmable period. When operating in 32-bit mode, the timer is split into two independent 32-
bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins,
TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are
connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a
requirement that software writes to the timer before the count expires, after which the count begins again.
If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be
set by programming the Reset Type Status Register (RSTYPE) (see Section 11.5.3.6) and the type of
reset initiated can set by programming the Reset Configuration Register (RSTCFG) (see
Section 11.5.3.8). For more information, see the KeyStone Architecture Timer 64P User's Guide
SPRUGV5.
11.20.2 Timers Electrical Timing
The tables and figures below describe the timing requirements and switching characteristics of the timers.
Table 11-60. Timer Input Timing Requirements⁽¹⁾
(see Figure 11-58)
NO.
1
t_w(TINPH)
2
t_w(TINPL)
Pulse duration, high
Pulse duration, low
(1) C = 1/SYSCLK1 clock frequency in ns
MIN
MAX UNIT
12C
ns
12C
ns
Table 11-61. Timer Output Switching Characteristics⁽¹⁾
(see Figure 11-58)
NO.
PARAMETER
3
t_w(TOUTH)
4
t_w(TOUTL)
Pulse duration, high
Pulse duration, low
(1) C = 1/SYSCLK1 clock frequency in ns.
MIN
12C - 3
12C - 3
MAX
UNIT
ns
ns
1
2
TIMIx
3
4
TIMOx
Figure 11-58. Timer Timing
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TCI6630K2L Peripheral Information and Electrical Specifications 273
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