TCI6630K2L Datasheet, PDF (292/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 11-76 summarizes the DEBUG core assignment. Emulation suspend output of all the cores are
synchronized to SYSCLK1/6 which is frequency of the slowest peripheral that uses these signals.
Core #
0..3
8,9
12..29
30
31
Table 11-76. EMUSUSP Core Summary(for EMUSUSP handshake to DEBUGSS)
Assignment
C66x CorePac0..3
ARM CorePac 0,1
Reserved
Logical OR of Core #0..11
Logical AND of Core #0..11
11.37.5 Advanced Event Triggering (AET)
The device supports advanced event triggering (AET). This capability can be used to debug complex
problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware program breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
292 TCI6630K2L Peripheral Information and Electrical Specifications
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TCI6630K2L