TCI6630K2L Datasheet, PDF (201/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

www.ti.com
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Figure 9-41. SerDes Reset Isolation (RSTISOCTL)
31
Reserved
R-n
Legend: R = Read only; -n = value after reset
2
1
SGMIIRSTISOEN
RW-0
0
AILRSTISOEN
RW-0
Bit
31-2
1
Field
Reserved
SGMIIRSTISOEN
0
AILRSTISOEN
Table 9-53. SerDes Reset Isolation Register Field Descriptions
Description
Reserved. Read only
SGMII SerDes lane reset isolation.
• 0 = SGMII SerDes lane reset isolation disabled for all lanes.
• 1 = SGMII SerDes lane reset isolation enabled for all lanes, i.e. serdes lanes will not be reset on Non-
POR chip resets.
AIL SerDes lane reset isolation.
• 0 = AIL SerDes lane reset isolation disabled for all lanes.
• 1 = AIL SerDes lane reset isolation enabled for all lanes, i.e. serdes lanes will not be reset on Non-POR
chip resets.
9.2.3.25 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
The registers defined in ARM Configuration Register 0 (ARMENDIAN_CFGr_0) and ARM Configuration
Register 1 (ARMENDIAN_CFGr_1) control the way Cortex-A15 processor core access to peripheral
MMRs shows up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant
view of the peripheral MMRs when performing a 32-bit access. (Only one of the eight register sets is
shown.)
Figure 9-42. ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
31
BASEADDR
RW
Legend: RW = Read/Write; R = Read only
87
0
Reserved
R-0000 0000
Table 9-54. ARM Endian Configuration Register 0
Default Values
ARM ENDIAN CONFIGURATION REGISTER 0
ARMENDIAN_CFG0_0
ARMENDIAN_CFG1_0
ARMENDIAN_CFG2_0
ARMENDIAN_CFG3_0
ARMENDIAN_CFG4_0
ARMENDIAN_CFG5_0
ARMENDIAN_CFG6_0
ARMENDIAN_CFG7_0
DEFAULT
VALUES
0x0001C000
0x00020000
0x000BC000
0x00210000
0x0023A000
0x00240000
0x01000000
0xFFFFFF00
Bit
31-8
Field
BASEADDR
7-0 Reserved
Table 9-55. ARM Endian Configuration Register 0 Field Descriptions
Description
24-bit Base Address of Configuration Region R
This base address defines the start of a contiguous block of Memory Mapped Register space for which a
word swap is done by the ARM CorePac bridge.
Reserved
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TCI6630K2L
Device Boot and Configuration 201