TCI6630K2L Datasheet, PDF (73/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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MASTER ID
162
163
164
165
166
167
168
168
169
170
171
172
173
174
175
176
177
178
179
180-183
184-255
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 7-6. Master ID Settings (continued)
TCI6630
Reserved
Reserved
CPT_EDMA3CC0
CPT_EDMA3CC1_2
CPT_INTC
CPT_SPI_ROM_EMIP16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPT_MSMC5
CPT_MSMC6
CPT_MSMC7
CPT_MSMC4
CPT_CFG_3P_U
Reserved
NETCP_GLOBAL0
Reserved
NOTE
There are two master ID values assigned to the Queue Manager_second master port, one
master ID for external linking RAM and the other one for the PDSP/MCDM accesses.
Table 7-7 shows the privilege ID of each C66x CorePac and everymastering peripheral. The table also
shows the privilege level (supervisor vs. user), security level (secure vs. non-secure), and access type
(instruction read vs. data/DMA read or write) of each master on the device. In some cases, a particular
setting depends on software being executed at the time of the access or the configuration of the master
peripheral.
PRIVILEGE
ID
MASTER
0
C66x CorePac0
1
C66x CorePac1
2
C66x CorePac2
3
C66x CorePac3
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
ARM CorePac
Table 7-7. Privilege ID Settings
PRIVILEGE LEVEL
SW dependent, driven by MSMC
SW dependent, driven by MSMC
SW dependent, driven by MSMC
SW dependent, driven by MSMC
SECURITY
LEVEL
Non-secure
Non-secure
Non-secure
Non-secure
ACCESS
TYPE
DMA
DMA
DMA
DMA
SW dependent
Non-secure DMA
Copyright © 2013–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for TCI6630K2L
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