TCI6630K2L Datasheet, PDF (1/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
TCI6630K2L Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
1 TCI6630K2L Features and Description
1.1 Features
1
• Four TMS320C66x DSP Core Subsystems (C66x
CorePacs), Each With
– 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
DSP Core
• 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
• 19.2 GFlops/Core for Floating Point @ 1.2
GHz
– Memory
• 32K Byte L1P Per CorePac
• 32K Byte L1D Per CorePac
• 1024K Byte Local L2 Per CorePac
• ARM CorePac
– Two ARM^® Cortex^®-A15 MPCore™ Processors
at Up to 1.2 GHz
– 1MB L2 Cache Memory Shared by Two ARM
Cores
– Full Implementation of ARMv7-A Architecture
Instruction Set
– 32KB L1 Instruction and Data Caches per Core
– AMBA 4.0 AXI Coherency Extension (ACE)
Master Port, Connected to MSMC for Low
Latency Access to Shared MSMC SRAM
• Multicore Shared Memory Controller (MSMC)
– 2 MB SRAM Memory Shared by Four DSP
CorePacs and One ARM CorePac
– Memory Protection Unit for Both MSM SRAM
and DDR3_EMIF
• On-chip Standalone RAM (OSR) - 1MB On-Chip
SRAM for Additional Shared Memory
• Hardware Coprocessors
– Two Turbo Decoders
• Supports WCDMA/HSPA/HSPA+/TD-
SCDMA, LTE, LTE-A and WiMAX
• Supports Up to 282 Mbps for LTE at Block
Size 6144, 8 Iterations and Up to 206 Mbps
for WCDMA at Block Size 5114, 8 Iterations
• Low DSP Overhead – HW Interleaver Table
Generation and CRC Check
– Four Viterbi Decoders
• Supports Up to 50 Mbps (Length 9, Rate 1/3,
Block Size 2500)
– One WCDMA Receive Acceleration
Coprocessors
• Supports Up to 8192 Correlators
– WCDMA Transmit Acceleration Coprocessor
• Supports Up to 2304 Spreaders
– Two Fast Fourier Transform Coprocessors
1
• Support Up to 1200 Mscps at FFT Size 1024
– Bit Rate Coprocessor
• WCDMA/HSPA+, TD-SCDMA, LTE, LTE-A
and WiMAX Uplink and Downlink Bit
Processing
• Includes Encoding, Rate
Matching/Dematching, Segmentation,
Multiplexing, and More
• Supports Up to DL 1525 Mbps and UL 1030
Mbsp for LTE and DL 784 Mbps and UL 216
Mbsp for WCDMA/TD-SCDMA
• Multicore Navigator
– 8k Multi-Purpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead
Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
• Transport Plane IPsec, GTP-U, SCTP,
PDCP
• L2 User Plane PDCP (RoHC, Air Ciphering)
• 1 Gbps Wire Speed Throughput at 1.5
MPackets Per Second
– Security Accelerator Engine Enables Support for
• IPSec, SRTP, 3GPP and WiMAX Air
Interface, and SSL/TLS Security
• ECB, CBC, CTR, F8, A5/3, CCM, GCM,
HMAC, CMAC, GMAC, AES, DES, 3DES,
Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
Hash), MD5, ZUC, ZUC-MAC
• Up to 6.4 Gbps IPSec and 3 Gbps Air
Ciphering
– Ethernet Subsystem
• Four SGMII Port Switch
• Eight Rake/Search Accelerators (RSA) for
– Chip Rate Processing for WCDMA Rel'99,
HSDPA, and HSDPA+
– Reed-Muller Decoding
• Peripherals
– Digital Front End (DFE) Subsystem
• Support up to Four Lane JESD204A/B (7.37
Gbps Line Rate Max.) Interface to Multiple
Data Converters
• Integration of Digital Down/Up-Conversion
(DDC/DUC), Crest Factor Reduction (CFR),
and Digital Pre-Distortion (DPD) Modules
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.